drm/i915: Move CUR SURFLIVE definition to a better place.

No functional change. But let's keep definitions clean
and cursor related register definitions together.

v2: Fix caps x no caps on same reg. Change name to match
    original reg name. (by Ville).
    Also fix name on code s/surlive/surflive and on subject
    s/cur_surlife/cur surflive/.

Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180312210528.7905-1-rodrigo.vivi@intel.com

drivers/gpu/drm/i915/i915_reg.h

@@ -6009,6 +6009,7 @@ enum {
 #define CURSIZE			_MMIO(0x700a0) /* 845/865 */
 #define _CUR_FBC_CTL_A		0x700a0 /* ivb+ */
 #define   CUR_FBC_CTL_EN	(1 << 31)
+#define _CURASURFLIVE		0x700ac /* g4x+ */
 #define _CURBCNTR		0x700c0
 #define _CURBBASE		0x700c4
 #define _CURBPOS		0x700c8
@@ -6025,16 +6026,14 @@ enum {
 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
 #define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
+#define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)
 
 #define CURSOR_A_OFFSET 0x70080
 #define CURSOR_B_OFFSET 0x700c0
 #define CHV_CURSOR_C_OFFSET 0x700e0
 #define IVB_CURSOR_B_OFFSET 0x71080
 #define IVB_CURSOR_C_OFFSET 0x72080
 
-#define _CUR_SURLIVE		0x700AC
-#define CUR_SURLIVE(pipe)	_CURSOR2(pipe, _CUR_SURLIVE)
-
 /* Display A control */
 #define _DSPACNTR				0x70180
 #define   DISPLAY_PLANE_ENABLE			(1<<31)

drivers/gpu/drm/i915/intel_psr.c

@@ -1044,11 +1044,11 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
 			 * This documented WA for bxt can be safely applied
 			 * broadly so we can force HW tracking to exit PSR
 			 * instead of disabling and re-enabling.
-			 * Workaround tells us to write 0 to CUR_SURLIVE_A,
+			 * Workaround tells us to write 0 to CUR_SURFLIVE_A,
 			 * but it makes more sense write to the current active
 			 * pipe.
 			 */
-			I915_WRITE(CUR_SURLIVE(pipe), 0);
+			I915_WRITE(CURSURFLIVE(pipe), 0);
 		}
 	}