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i2c: img-scb: remove fifo EMPTYING interrupts handle
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Now that we are using the transaction halt interrupt to safely control
repeated start transfers, we no longer need to handle the fifo
emptying interrupts.

Handling this interrupt along with Transaction Halt interrupt can
cause erratic behaviour.

Signed-off-by: Sifan Naeem <sifan.naeem@imgtec.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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Sifan Naeem authored and Wolfram Sang committed Jan 2, 2016
1 parent c55ebe0 commit a8c5a8d
Showing 1 changed file with 3 additions and 13 deletions.
16 changes: 3 additions & 13 deletions drivers/i2c/busses/i2c-img-scb.c
Original file line number Diff line number Diff line change
Expand Up @@ -154,7 +154,6 @@
#define INT_TIMING BIT(18)

#define INT_FIFO_FULL_FILLING (INT_FIFO_FULL | INT_FIFO_FILLING)
#define INT_FIFO_EMPTY_EMPTYING (INT_FIFO_EMPTY | INT_FIFO_EMPTYING)

/* Level interrupts need clearing after handling instead of before */
#define INT_LEVEL 0x01e00
Expand All @@ -176,8 +175,7 @@
INT_WRITE_ACK_ERR | \
INT_FIFO_FULL | \
INT_FIFO_FILLING | \
INT_FIFO_EMPTY | \
INT_FIFO_EMPTYING)
INT_FIFO_EMPTY)

#define INT_ENABLE_MASK_WAITSTOP (INT_SLAVE_EVENT | \
INT_ADDR_ACK_ERR | \
Expand Down Expand Up @@ -874,16 +872,8 @@ static unsigned int img_i2c_auto(struct img_i2c *i2c,
return ISR_WAITSTOP;
}
} else {
if (int_status & INT_FIFO_EMPTY_EMPTYING) {
/*
* The write fifo empty indicates that we're in the
* last byte so it's safe to start a new write
* transaction without losing any bytes from the
* previous one.
* see 2.3.7 Repeated Start Transactions.
*/
if ((int_status & INT_FIFO_EMPTY) &&
i2c->msg.len == 0)
if (int_status & INT_FIFO_EMPTY) {
if (i2c->msg.len == 0)
return ISR_WAITSTOP;
img_i2c_write_fifo(i2c);
}
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