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bus: ti-sysc: Fix 1-wire reset quirk
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Because of the i2c quirk we have the reset quirks named in a confusing
way. Let's fix the 1-wire quirk accordinlyg. Then let's switch to using
better naming later on.

Fixes: 4e23be4 ("bus: ti-sysc: Add support for module specific reset quirks")
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Tony Lindgren committed Feb 26, 2020
1 parent bb6d3fb commit aec551c
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions drivers/bus/ti-sysc.c
Original file line number Diff line number Diff line change
Expand Up @@ -1400,7 +1400,7 @@ static void sysc_init_revision_quirks(struct sysc *ddata)
}

/* 1-wire needs module's internal clocks enabled for reset */
static void sysc_clk_enable_quirk_hdq1w(struct sysc *ddata)
static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata)
{
int offset = 0x0c; /* HDQ_CTRL_STATUS */
u16 val;
Expand Down Expand Up @@ -1488,7 +1488,7 @@ static void sysc_init_module_quirks(struct sysc *ddata)
return;

if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
ddata->clk_enable_quirk = sysc_clk_enable_quirk_hdq1w;
ddata->clk_disable_quirk = sysc_pre_reset_quirk_hdq1w;

return;
}
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