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Merge branches 'apple/dart', 'arm/mediatek', 'arm/msm', 'arm/smmu', '…
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…ppc/pamu', 'x86/vt-d', 'x86/amd' and 'vfio-notifier-fix' into next
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Joerg Roedel committed May 20, 2022
8 parents ee53543 + de78657 + 8b9ad48 + b11deb2 + cae8d1f + 0d647b3 + 42bb5aa + fa7e9ec commit b0dacee
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3 changes: 3 additions & 0 deletions .mailmap
Original file line number Diff line number Diff line change
Expand Up @@ -45,6 +45,7 @@ Andrey Konovalov <andreyknvl@gmail.com> <andreyknvl@google.com>
Andrey Ryabinin <ryabinin.a.a@gmail.com> <a.ryabinin@samsung.com>
Andrey Ryabinin <ryabinin.a.a@gmail.com> <aryabinin@virtuozzo.com>
Andrzej Hajda <andrzej.hajda@intel.com> <a.hajda@samsung.com>
André Almeida <andrealmeid@igalia.com> <andrealmeid@collabora.com>
Andy Adamson <andros@citi.umich.edu>
Antoine Tenart <atenart@kernel.org> <antoine.tenart@bootlin.com>
Antoine Tenart <atenart@kernel.org> <antoine.tenart@free-electrons.com>
Expand Down Expand Up @@ -204,6 +205,7 @@ Juha Yrjola <at solidboot.com>
Juha Yrjola <juha.yrjola@nokia.com>
Juha Yrjola <juha.yrjola@solidboot.com>
Julien Thierry <julien.thierry.kdev@gmail.com> <julien.thierry@arm.com>
Kalle Valo <kvalo@kernel.org> <kvalo@codeaurora.org>
Kalyan Thota <quic_kalyant@quicinc.com> <kalyan_t@codeaurora.org>
Kay Sievers <kay.sievers@vrfy.org>
Kees Cook <keescook@chromium.org> <kees.cook@canonical.com>
Expand Down Expand Up @@ -249,6 +251,7 @@ Mark Yao <markyao0591@gmail.com> <mark.yao@rock-chips.com>
Martin Kepplinger <martink@posteo.de> <martin.kepplinger@ginzinger.com>
Martin Kepplinger <martink@posteo.de> <martin.kepplinger@puri.sm>
Martin Kepplinger <martink@posteo.de> <martin.kepplinger@theobroma-systems.com>
Martyna Szapar-Mudlaw <martyna.szapar-mudlaw@linux.intel.com> <martyna.szapar-mudlaw@intel.com>
Mathieu Othacehe <m.othacehe@gmail.com>
Matthew Wilcox <willy@infradead.org> <matthew.r.wilcox@intel.com>
Matthew Wilcox <willy@infradead.org> <matthew@wil.cx>
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4 changes: 2 additions & 2 deletions Documentation/arm64/memory-tagging-extension.rst
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Expand Up @@ -228,10 +228,10 @@ Core dump support
-----------------

The allocation tags for user memory mapped with ``PROT_MTE`` are dumped
in the core file as additional ``PT_ARM_MEMTAG_MTE`` segments. The
in the core file as additional ``PT_AARCH64_MEMTAG_MTE`` segments. The
program header for such segment is defined as:

:``p_type``: ``PT_ARM_MEMTAG_MTE``
:``p_type``: ``PT_AARCH64_MEMTAG_MTE``
:``p_flags``: 0
:``p_offset``: segment file offset
:``p_vaddr``: segment virtual address, same as the corresponding
Expand Down
3 changes: 3 additions & 0 deletions Documentation/arm64/silicon-errata.rst
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Expand Up @@ -189,6 +189,9 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| Qualcomm Tech. | Kryo4xx Silver | N/A | ARM64_ERRATUM_1024718 |
+----------------+-----------------+-----------------+-----------------------------+
| Qualcomm Tech. | Kryo4xx Gold | N/A | ARM64_ERRATUM_1286807 |
+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+
| Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 |
+----------------+-----------------+-----------------+-----------------------------+
4 changes: 0 additions & 4 deletions Documentation/devicetree/bindings/clock/imx8m-clock.yaml
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Expand Up @@ -55,8 +55,6 @@ allOf:
then:
properties:
clocks:
minItems: 7
maxItems: 7
items:
- description: 32k osc
- description: 25m osc
Expand All @@ -66,8 +64,6 @@ allOf:
- description: ext3 clock input
- description: ext4 clock input
clock-names:
minItems: 7
maxItems: 7
items:
- const: ckil
- const: osc_25m
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13 changes: 11 additions & 2 deletions Documentation/devicetree/bindings/clock/microchip,mpfs.yaml
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Expand Up @@ -22,7 +22,16 @@ properties:
const: microchip,mpfs-clkcfg

reg:
maxItems: 1
items:
- description: |
clock config registers:
These registers contain enable, reset & divider tables for the, cpu,
axi, ahb and rtc/mtimer reference clocks as well as enable and reset
for the peripheral clocks.
- description: |
mss pll dri registers:
Block of registers responsible for dynamic reconfiguration of the mss
pll
clocks:
maxItems: 1
Expand Down Expand Up @@ -51,7 +60,7 @@ examples:
#size-cells = <2>;
clkcfg: clock-controller@20002000 {
compatible = "microchip,mpfs-clkcfg";
reg = <0x0 0x20002000 0x0 0x1000>;
reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
clocks = <&ref>;
#clock-cells = <1>;
};
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Original file line number Diff line number Diff line change
Expand Up @@ -95,7 +95,6 @@ then:
properties:
clocks:
minItems: 1
maxItems: 4
items:
- description: Functional clock
- description: EXTAL input clock
Expand All @@ -104,7 +103,6 @@ then:

clock-names:
minItems: 1
maxItems: 4
items:
- const: fck
# The LVDS encoder can use the EXTAL or DU_DOTCLKINx clocks.
Expand All @@ -128,12 +126,10 @@ then:
else:
properties:
clocks:
maxItems: 1
items:
- description: Functional clock

clock-names:
maxItems: 1
items:
- const: fck

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23 changes: 0 additions & 23 deletions Documentation/devicetree/bindings/display/renesas,du.yaml
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Expand Up @@ -109,15 +109,13 @@ allOf:
properties:
clocks:
minItems: 1
maxItems: 3
items:
- description: Functional clock
- description: DU_DOTCLKIN0 input clock
- description: DU_DOTCLKIN1 input clock

clock-names:
minItems: 1
maxItems: 3
items:
- const: du.0
- pattern: '^dclkin\.[01]$'
Expand Down Expand Up @@ -159,7 +157,6 @@ allOf:
properties:
clocks:
minItems: 2
maxItems: 4
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
Expand All @@ -168,7 +165,6 @@ allOf:

clock-names:
minItems: 2
maxItems: 4
items:
- const: du.0
- const: du.1
Expand Down Expand Up @@ -216,7 +212,6 @@ allOf:
properties:
clocks:
minItems: 2
maxItems: 4
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
Expand All @@ -225,7 +220,6 @@ allOf:

clock-names:
minItems: 2
maxItems: 4
items:
- const: du.0
- const: du.1
Expand Down Expand Up @@ -271,7 +265,6 @@ allOf:
properties:
clocks:
minItems: 2
maxItems: 4
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
Expand All @@ -280,7 +273,6 @@ allOf:

clock-names:
minItems: 2
maxItems: 4
items:
- const: du.0
- const: du.1
Expand Down Expand Up @@ -327,7 +319,6 @@ allOf:
properties:
clocks:
minItems: 2
maxItems: 4
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
Expand All @@ -336,7 +327,6 @@ allOf:

clock-names:
minItems: 2
maxItems: 4
items:
- const: du.0
- const: du.1
Expand Down Expand Up @@ -386,7 +376,6 @@ allOf:
properties:
clocks:
minItems: 3
maxItems: 6
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
Expand All @@ -397,7 +386,6 @@ allOf:

clock-names:
minItems: 3
maxItems: 6
items:
- const: du.0
- const: du.1
Expand Down Expand Up @@ -448,7 +436,6 @@ allOf:
properties:
clocks:
minItems: 4
maxItems: 8
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
Expand All @@ -461,7 +448,6 @@ allOf:

clock-names:
minItems: 4
maxItems: 8
items:
- const: du.0
- const: du.1
Expand Down Expand Up @@ -525,7 +511,6 @@ allOf:
properties:
clocks:
minItems: 3
maxItems: 6
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
Expand All @@ -536,7 +521,6 @@ allOf:

clock-names:
minItems: 3
maxItems: 6
items:
- const: du.0
- const: du.1
Expand Down Expand Up @@ -596,7 +580,6 @@ allOf:
properties:
clocks:
minItems: 3
maxItems: 6
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
Expand All @@ -607,7 +590,6 @@ allOf:

clock-names:
minItems: 3
maxItems: 6
items:
- const: du.0
- const: du.1
Expand Down Expand Up @@ -666,14 +648,12 @@ allOf:
properties:
clocks:
minItems: 1
maxItems: 2
items:
- description: Functional clock for DU0
- description: DU_DOTCLKIN0 input clock

clock-names:
minItems: 1
maxItems: 2
items:
- const: du.0
- const: dclkin.0
Expand Down Expand Up @@ -723,7 +703,6 @@ allOf:
properties:
clocks:
minItems: 2
maxItems: 4
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
Expand All @@ -732,7 +711,6 @@ allOf:

clock-names:
minItems: 2
maxItems: 4
items:
- const: du.0
- const: du.1
Expand Down Expand Up @@ -791,7 +769,6 @@ allOf:
- description: Functional clock

clock-names:
maxItems: 1
items:
- const: du.0

Expand Down
7 changes: 3 additions & 4 deletions Documentation/devicetree/bindings/hwmon/ti,tmp421.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -58,10 +58,9 @@ patternProperties:
description: |
The value (two's complement) to be programmed in the channel specific N correction register.
For remote channels only.
$ref: /schemas/types.yaml#/definitions/uint32
items:
minimum: 0
maximum: 255
$ref: /schemas/types.yaml#/definitions/int32
minimum: -128
maximum: 127

required:
- reg
Expand Down
2 changes: 0 additions & 2 deletions Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -138,7 +138,6 @@ allOf:
- const: bus
- const: adc
minItems: 1
maxItems: 2

interrupts:
items:
Expand Down Expand Up @@ -170,7 +169,6 @@ allOf:
- const: bus
- const: adc
minItems: 1
maxItems: 2

interrupts:
items:
Expand Down
25 changes: 23 additions & 2 deletions Documentation/devicetree/bindings/iommu/arm,smmu.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -37,8 +37,10 @@ properties:
- qcom,sc7180-smmu-500
- qcom,sc7280-smmu-500
- qcom,sc8180x-smmu-500
- qcom,sc8280xp-smmu-500
- qcom,sdm845-smmu-500
- qcom,sdx55-smmu-500
- qcom,sdx65-smmu-500
- qcom,sm6350-smmu-500
- qcom,sm8150-smmu-500
- qcom,sm8250-smmu-500
Expand All @@ -62,8 +64,9 @@ properties:
for improved performance.
items:
- enum:
- nvidia,tegra194-smmu
- nvidia,tegra186-smmu
- nvidia,tegra194-smmu
- nvidia,tegra234-smmu
- const: nvidia,smmu-500
- items:
- const: arm,mmu-500
Expand Down Expand Up @@ -157,6 +160,17 @@ properties:
power-domains:
maxItems: 1

nvidia,memory-controller:
description: |
A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
The memory controller needs to be programmed with a mapping of memory
client IDs to ARM SMMU stream IDs.
If this property is absent, the mapping programmed by early firmware
will be used and it is not guaranteed that IOMMU translations will be
enabled for any given device.
$ref: /schemas/types.yaml#/definitions/phandle

required:
- compatible
- reg
Expand All @@ -172,13 +186,20 @@ allOf:
compatible:
contains:
enum:
- nvidia,tegra194-smmu
- nvidia,tegra186-smmu
- nvidia,tegra194-smmu
- nvidia,tegra234-smmu
then:
properties:
reg:
minItems: 1
maxItems: 2

# The reference to the memory controller is required to ensure that the
# memory client to stream ID mapping can be done synchronously with the
# IOMMU attachment.
required:
- nvidia,memory-controller
else:
properties:
reg:
Expand Down
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