ARM: dts: mvebu: move all peripherals inside soc

reorganize the .dts and .dtsi files so that all devices are under the
soc { } node (currently some devices such as the interrupt controller,
the L2 cache and a few others are outside).

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

arch/arm/boot/dts/armada-370-xp.dtsi

@@ -28,26 +28,26 @@
 		};
 	};
 
-	mpic: interrupt-controller@d0020000 {
-	      compatible = "marvell,mpic";
-	      #interrupt-cells = <1>;
-	      #size-cells = <1>;
-	      interrupt-controller;
-	};
-
-	coherency-fabric@d0020200 {
-		compatible = "marvell,coherency-fabric";
-		reg = <0xd0020200 0xb0>,
-		      <0xd0021810 0x1c>;
-	};
-
 	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "simple-bus";
 		interrupt-parent = <&mpic>;
 		ranges;
 
+		mpic: interrupt-controller@d0020000 {
+			compatible = "marvell,mpic";
+			#interrupt-cells = <1>;
+			#size-cells = <1>;
+			interrupt-controller;
+		};
+
+		coherency-fabric@d0020200 {
+			compatible = "marvell,coherency-fabric";
+			reg = <0xd0020200 0xb0>,
+			      <0xd0021810 0x1c>;
+		};
+
 		serial@d0012000 {
 				compatible = "snps,dw-apb-uart";
 				reg = <0xd0012000 0x100>;

arch/arm/boot/dts/armada-370.dtsi

@@ -20,30 +20,31 @@
 / {
 	model = "Marvell Armada 370 family SoC";
 	compatible = "marvell,armada370", "marvell,armada-370-xp";
-	L2: l2-cache {
-		compatible = "marvell,aurora-outer-cache";
-		reg = <0xd0008000 0x1000>;
-		cache-id-part = <0x100>;
-		wt-override;
-	};
 
 	aliases {
 		gpio0 = &gpio0;
 		gpio1 = &gpio1;
 		gpio2 = &gpio2;
 	};
 
-	mpic: interrupt-controller@d0020000 {
-	      reg = <0xd0020a00 0x1d0>,
-		    <0xd0021870 0x58>;
-	};
-
 	soc {
+		mpic: interrupt-controller@d0020000 {
+			reg = <0xd0020a00 0x1d0>,
+			      <0xd0021870 0x58>;
+		};
+
 		system-controller@d0018200 {
 				compatible = "marvell,armada-370-xp-system-controller";
 				reg = <0xd0018200 0x100>;
 		};
 
+		L2: l2-cache {
+			compatible = "marvell,aurora-outer-cache";
+			reg = <0xd0008000 0x1000>;
+			cache-id-part = <0x100>;
+			wt-override;
+		};
+
 		pinctrl {
 			compatible = "marvell,mv88f6710-pinctrl";
 			reg = <0xd0018000 0x38>;

arch/arm/boot/dts/armada-xp.dtsi

@@ -22,25 +22,25 @@
 	model = "Marvell Armada XP family SoC";
 	compatible = "marvell,armadaxp", "marvell,armada-370-xp";
 
-	L2: l2-cache {
-		compatible = "marvell,aurora-system-cache";
-		reg = <0xd0008000 0x1000>;
-		cache-id-part = <0x100>;
-		wt-override;
-	};
+	soc {
+		L2: l2-cache {
+			compatible = "marvell,aurora-system-cache";
+			reg = <0xd0008000 0x1000>;
+			cache-id-part = <0x100>;
+			wt-override;
+		};
 
-	mpic: interrupt-controller@d0020000 {
-	      reg = <0xd0020a00 0x2d0>,
-		    <0xd0021070 0x58>;
-	};
+		mpic: interrupt-controller@d0020000 {
+		      reg = <0xd0020a00 0x2d0>,
+			    <0xd0021070 0x58>;
+		};
 
-	armada-370-xp-pmsu@d0022000 {
-		compatible = "marvell,armada-370-xp-pmsu";
-		reg = <0xd0022100 0x430>,
-		      <0xd0020800 0x20>;
-	};
+		armada-370-xp-pmsu@d0022000 {
+			compatible = "marvell,armada-370-xp-pmsu";
+			reg = <0xd0022100 0x430>,
+			      <0xd0020800 0x20>;
+		};
 
-	soc {
 		serial@d0012200 {
 				compatible = "snps,dw-apb-uart";
 				reg = <0xd0012200 0x100>;