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Add support of the device tree probing for the Renesas SH-Mobile SoCs documenting the device tree binding as necessary. This work is loosely based on the original patch by Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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* Renesas Electronics SH EtherMAC | ||
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This file provides information on what the device node for the SH EtherMAC | ||
interface contains. | ||
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Required properties: | ||
- compatible: "renesas,gether-r8a7740" if the device is a part of R8A7740 SoC. | ||
"renesas,ether-r8a7778" if the device is a part of R8A7778 SoC. | ||
"renesas,ether-r8a7779" if the device is a part of R8A7779 SoC. | ||
"renesas,ether-r8a7790" if the device is a part of R8A7790 SoC. | ||
"renesas,ether-r8a7791" if the device is a part of R8A7791 SoC. | ||
"renesas,ether-r7s72100" if the device is a part of R7S72100 SoC. | ||
- reg: offset and length of (1) the E-DMAC/feLic register block (required), | ||
(2) the TSU register block (optional). | ||
- interrupts: interrupt specifier for the sole interrupt. | ||
- phy-mode: see ethernet.txt file in the same directory. | ||
- phy-handle: see ethernet.txt file in the same directory. | ||
- #address-cells: number of address cells for the MDIO bus, must be equal to 1. | ||
- #size-cells: number of size cells on the MDIO bus, must be equal to 0. | ||
- clocks: clock phandle and specifier pair. | ||
- pinctrl-0: phandle, referring to a default pin configuration node. | ||
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Optional properties: | ||
- interrupt-parent: the phandle for the interrupt controller that services | ||
interrupts for this device. | ||
- pinctrl-names: pin configuration state name ("default"). | ||
- renesas,no-ether-link: boolean, specify when a board does not provide a proper | ||
Ether LINK signal. | ||
- renesas,ether-link-active-low: boolean, specify when the Ether LINK signal is | ||
active-low instead of normal active-high. | ||
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Example (Lager board): | ||
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ethernet@ee700000 { | ||
compatible = "renesas,ether-r8a7790"; | ||
reg = <0 0xee700000 0 0x400>; | ||
interrupt-parent = <&gic>; | ||
interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; | ||
clocks = <&mstp8_clks R8A7790_CLK_ETHER>; | ||
phy-mode = "rmii"; | ||
phy-handle = <&phy1>; | ||
pinctrl-0 = <ðer_pins>; | ||
pinctrl-names = "default"; | ||
renesas,ether-link-active-low; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
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phy1: ethernet-phy@1 { | ||
reg = <1>; | ||
interrupt-parent = <&irqc0>; | ||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>; | ||
pinctrl-0 = <&phy1_pins>; | ||
pinctrl-names = "default"; | ||
}; | ||
}; |
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