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drm/nouveau: pmu: Change the init value of elpg_disable_depth to 1
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ELPG will be enabled by default when GPMU finishes booting, which
means refcount "elpg_disable_depth" will get decreased by 1.
So to keep this counter to 0 when nobody enable/disable ELPG, set
it's initial value to 1.

Also this patch removes the codes in pmu's .fini function, to set
"elpg_disable_depth" to 0. This doesn't make much sense because
"elpg_disable_depth" will be set to 1 in .init later.

BUG=none
TEST=Boots to UI OK

Change-Id: Iff1d68f095fcd47eaca1a4c037c477a25ae2c7a7
Signed-off-by: Mark Zhang <markz@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/305621
Reviewed-by: Tomasz Figa <tfiga@chromium.org>
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Mark Zhang authored and chrome-bot committed Oct 27, 2015
1 parent 7b17ca9 commit b575426
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Showing 2 changed files with 10 additions and 9 deletions.
10 changes: 5 additions & 5 deletions drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c
Original file line number Diff line number Diff line change
Expand Up @@ -3171,7 +3171,11 @@ gk20a_pmu_init(struct nvkm_object *object)
nvkm_timer_alarm(priv, PMU_DVFS_INTERVAL, &priv->alarm);

mutex_lock(&priv->elpg_mutex);
priv->elpg_disable_depth = 0;
/*
* ELPG will be enabled when PMU finishes booting, so setting the
* counter to 1 initialy.
*/
priv->elpg_disable_depth = 1;
mutex_unlock(&priv->elpg_mutex);

mutex_lock(&priv->clk_gating_mutex);
Expand All @@ -3193,10 +3197,6 @@ gk20a_pmu_fini(struct nvkm_object *object, bool suspend)
cancel_work_sync(&priv->base.recv.work);
cancel_work_sync(&priv->pg_init);

mutex_lock(&priv->elpg_mutex);
priv->elpg_disable_depth = 0;
mutex_unlock(&priv->elpg_mutex);

mutex_lock(&priv->clk_gating_mutex);
priv->clk_gating_disable_depth = 0;
mutex_unlock(&priv->clk_gating_mutex);
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9 changes: 5 additions & 4 deletions drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c
Original file line number Diff line number Diff line change
Expand Up @@ -2613,9 +2613,6 @@ gm20b_pmu_fini(struct nvkm_object *object, bool suspend)
gk20a_pmu_enable(priv, pmc, false);
priv->isr_enabled = false;
mutex_unlock(&priv->isr_mutex);
mutex_lock(&priv->elpg_mutex);
priv->elpg_disable_depth = 0;
mutex_unlock(&priv->elpg_mutex);
priv->pmu_state = PMU_STATE_OFF;
mutex_lock(&priv->clk_gating_mutex);
priv->clk_gating_disable_depth = 0;
Expand Down Expand Up @@ -2692,7 +2689,11 @@ gm20b_pmu_init(struct nvkm_object *object) {
priv->pmu_setup_elpg = gm20b_pmu_setup_elpg;

mutex_lock(&priv->elpg_mutex);
priv->elpg_disable_depth = 0;
/*
* ELPG will be enabled when PMU finishes booting, so setting the
* counter to 1 initialy.
*/
priv->elpg_disable_depth = 1;
mutex_unlock(&priv->elpg_mutex);

mutex_lock(&priv->clk_gating_mutex);
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