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perf vendor events: Update SkylakeX events to v1.21
- Update SkylakeX events to v1.21. - Update SkylakeX JSON metrics from TMAM 4.0. Other fixes: - Add NO_NMI_WATCHDOG metric constraint to Backend_Bound - Fix misspelled error Signed-off-by: Jin Yao <yao.jin@linux.intel.com> Reviewed-by: Andi Kleen <ak@linux.intel.com> Acked-by: Ian Rogers <irogers@google.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kan Liang <kan.liang@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Link: https://lore.kernel.org/lkml/20200922031918.3723-1-yao.jin@linux.intel.com/ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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Sep 28, 2020
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tools/perf/pmu-events/arch/x86/skylakex/cache.json
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tools/perf/pmu-events/arch/x86/skylakex/floating-point.json
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,85 +1,85 @@ | ||
| [ | ||
| { | ||
| "EventCode": "0xC7", | ||
| "UMask": "0x1", | ||
| "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", | ||
| "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT14 RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", | ||
| "Counter": "0,1,2,3", | ||
| "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", | ||
| "CounterHTOff": "0,1,2,3,4,5,6,7", | ||
| "EventCode": "0xC7", | ||
| "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", | ||
| "SampleAfterValue": "2000003", | ||
| "CounterHTOff": "0,1,2,3,4,5,6,7" | ||
| "UMask": "0x4" | ||
| }, | ||
| { | ||
| "EventCode": "0xC7", | ||
| "UMask": "0x2", | ||
| "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", | ||
| "BriefDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.", | ||
| "Counter": "0,1,2,3", | ||
| "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", | ||
| "CounterHTOff": "0,1,2,3,4,5,6,7", | ||
| "EventCode": "0xC7", | ||
| "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", | ||
| "SampleAfterValue": "2000003", | ||
| "CounterHTOff": "0,1,2,3,4,5,6,7" | ||
| "UMask": "0x40" | ||
| }, | ||
| { | ||
| "EventCode": "0xC7", | ||
| "UMask": "0x4", | ||
| "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", | ||
| "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", | ||
| "Counter": "0,1,2,3", | ||
| "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", | ||
| "CounterHTOff": "0,1,2,3,4,5,6,7", | ||
| "EventCode": "0xC7", | ||
| "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", | ||
| "SampleAfterValue": "2000003", | ||
| "CounterHTOff": "0,1,2,3,4,5,6,7" | ||
| "UMask": "0x2" | ||
| }, | ||
| { | ||
| "EventCode": "0xC7", | ||
| "UMask": "0x8", | ||
| "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", | ||
| "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", | ||
| "Counter": "0,1,2,3", | ||
| "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", | ||
| "CounterHTOff": "0,1,2,3,4,5,6,7", | ||
| "EventCode": "0xC7", | ||
| "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", | ||
| "SampleAfterValue": "2000003", | ||
| "CounterHTOff": "0,1,2,3,4,5,6,7" | ||
| "UMask": "0x10" | ||
| }, | ||
| { | ||
| "EventCode": "0xC7", | ||
| "UMask": "0x10", | ||
| "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", | ||
| "BriefDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 16 calculations per element.", | ||
| "Counter": "0,1,2,3", | ||
| "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", | ||
| "CounterHTOff": "0,1,2,3,4,5,6,7", | ||
| "EventCode": "0xC7", | ||
| "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", | ||
| "SampleAfterValue": "2000003", | ||
| "CounterHTOff": "0,1,2,3,4,5,6,7" | ||
| "UMask": "0x80" | ||
| }, | ||
| { | ||
| "EventCode": "0xC7", | ||
| "UMask": "0x20", | ||
| "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", | ||
| "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", | ||
| "Counter": "0,1,2,3", | ||
| "CounterHTOff": "0,1,2,3,4,5,6,7", | ||
| "EventCode": "0xC7", | ||
| "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", | ||
| "SampleAfterValue": "2000003", | ||
| "CounterHTOff": "0,1,2,3,4,5,6,7" | ||
| "UMask": "0x20" | ||
| }, | ||
| { | ||
| "EventCode": "0xC7", | ||
| "UMask": "0x40", | ||
| "BriefDescription": "Number of Packed Double-Precision FP arithmetic instructions (Use operation multiplier of 8)", | ||
| "BriefDescription": "Cycles with any input/output SSE or FP assist", | ||
| "Counter": "0,1,2,3", | ||
| "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", | ||
| "SampleAfterValue": "2000003", | ||
| "CounterHTOff": "0,1,2,3,4,5,6,7" | ||
| "CounterHTOff": "0,1,2,3,4,5,6,7", | ||
| "CounterMask": "1", | ||
| "EventCode": "0xCA", | ||
| "EventName": "FP_ASSIST.ANY", | ||
| "PublicDescription": "Counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.", | ||
| "SampleAfterValue": "100003", | ||
| "UMask": "0x1e" | ||
| }, | ||
| { | ||
| "EventCode": "0xC7", | ||
| "UMask": "0x80", | ||
| "BriefDescription": "Number of Packed Single-Precision FP arithmetic instructions (Use operation multiplier of 16)", | ||
| "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", | ||
| "Counter": "0,1,2,3", | ||
| "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", | ||
| "CounterHTOff": "0,1,2,3,4,5,6,7", | ||
| "EventCode": "0xC7", | ||
| "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", | ||
| "SampleAfterValue": "2000003", | ||
| "CounterHTOff": "0,1,2,3,4,5,6,7" | ||
| "UMask": "0x1" | ||
| }, | ||
| { | ||
| "EventCode": "0xCA", | ||
| "UMask": "0x1e", | ||
| "BriefDescription": "Cycles with any input/output SSE or FP assist", | ||
| "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", | ||
| "Counter": "0,1,2,3", | ||
| "EventName": "FP_ASSIST.ANY", | ||
| "CounterMask": "1", | ||
| "PublicDescription": "Counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.", | ||
| "SampleAfterValue": "100003", | ||
| "CounterHTOff": "0,1,2,3,4,5,6,7" | ||
| "CounterHTOff": "0,1,2,3,4,5,6,7", | ||
| "EventCode": "0xC7", | ||
| "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", | ||
| "SampleAfterValue": "2000003", | ||
| "UMask": "0x8" | ||
| } | ||
| ] |
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