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drm/i915/gt: Only wait for register chipset flush if active
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Only serialise with the chipset using an mmio if the chipset is
currently active. We expect that any writes into the chipset range will
simply be forgotten until it wakes up.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191118184943.2593048-8-chris@chris-wilson.co.uk
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Chris Wilson committed Nov 19, 2019
1 parent d147483 commit b642269
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion drivers/gpu/drm/i915/gt/intel_gt.c
Original file line number Diff line number Diff line change
Expand Up @@ -304,7 +304,7 @@ void intel_gt_flush_ggtt_writes(struct intel_gt *gt)

intel_gt_chipset_flush(gt);

with_intel_runtime_pm(uncore->rpm, wakeref) {
with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref) {
unsigned long flags;

spin_lock_irqsave(&uncore->lock, flags);
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