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dt-bindings: reset: Add YAML schemas for the Intel Reset controller
Add YAML schemas for the reset controller on Intel Gateway SoC. Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: System Reset Controller on Intel Gateway SoCs | ||
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maintainers: | ||
- Dilip Kota <eswara.kota@linux.intel.com> | ||
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properties: | ||
compatible: | ||
enum: | ||
- intel,rcu-lgm | ||
- intel,rcu-xrx200 | ||
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reg: | ||
description: Reset controller registers. | ||
maxItems: 1 | ||
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intel,global-reset: | ||
description: Global reset register offset and bit offset. | ||
allOf: | ||
- $ref: /schemas/types.yaml#/definitions/uint32-array | ||
- maxItems: 2 | ||
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"#reset-cells": | ||
minimum: 2 | ||
maximum: 3 | ||
description: | | ||
First cell is reset request register offset. | ||
Second cell is bit offset in reset request register. | ||
Third cell is bit offset in reset status register. | ||
For LGM SoC, reset cell count is 2 as bit offset in | ||
reset request and reset status registers is same. Whereas | ||
3 for legacy SoCs as bit offset differs. | ||
required: | ||
- compatible | ||
- reg | ||
- intel,global-reset | ||
- "#reset-cells" | ||
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additionalProperties: false | ||
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examples: | ||
- | | ||
rcu0: reset-controller@e0000000 { | ||
compatible = "intel,rcu-lgm"; | ||
reg = <0xe0000000 0x20000>; | ||
intel,global-reset = <0x10 30>; | ||
#reset-cells = <2>; | ||
}; | ||
pwm: pwm@e0d00000 { | ||
status = "disabled"; | ||
compatible = "intel,lgm-pwm"; | ||
reg = <0xe0d00000 0x30>; | ||
clocks = <&cgu0 1>; | ||
#pwm-cells = <2>; | ||
resets = <&rcu0 0x30 21>; | ||
}; |