Staging: et131x: put the jagcore routines in with their users

We have two trivial IRQ routines, a single statement and a real function -
relocate them. While we are at it kill the trivial to sort out soft reset
and slv bits in the same areas of code.

Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

drivers/staging/et131x/Makefile

@@ -5,7 +5,6 @@
 obj-$(CONFIG_ET131X) += et131x.o
 
 et131x-objs :=	et1310_eeprom.o \
-		et1310_jagcore.o \
 		et1310_mac.o \
 		et1310_phy.o \
 		et1310_pm.o \

drivers/staging/et131x/et1310_address_map.h

@@ -116,52 +116,20 @@
  */
 
 /*
- * structure for software reset reg in global address map
- * located at address 0x0028
+ * Software reset reg at address 0x0028
+ * 0: 	txdma_sw_reset
+ * 1:	rxdma_sw_reset
+ * 2:	txmac_sw_reset
+ * 3:	rxmac_sw_reset
+ * 4:	mac_sw_reset
+ * 5:	mac_stat_sw_reset
+ * 6:	mmc_sw_reset
+ *31:	selfclr_disable
  */
-typedef union _SW_RESET_t {
-	u32 value;
-	struct {
-#ifdef _BIT_FIELDS_HTOL
-		u32 selfclr_disable:1;	/* bit 31 */
-		u32 unused:24;		/* bits 7-30 */
-		u32 mmc_sw_reset:1;	/* bit 6 */
-		u32 mac_stat_sw_reset:1;	/* bit 5 */
-		u32 mac_sw_reset:1;	/* bit 4 */
-		u32 rxmac_sw_reset:1;	/* bit 3 */
-		u32 txmac_sw_reset:1;	/* bit 2 */
-		u32 rxdma_sw_reset:1;	/* bit 1 */
-		u32 txdma_sw_reset:1;	/* bit 0 */
-#else
-		u32 txdma_sw_reset:1;	/* bit 0 */
-		u32 rxdma_sw_reset:1;	/* bit 1 */
-		u32 txmac_sw_reset:1;	/* bit 2 */
-		u32 rxmac_sw_reset:1;	/* bit 3 */
-		u32 mac_sw_reset:1;	/* bit 4 */
-		u32 mac_stat_sw_reset:1;	/* bit 5 */
-		u32 mmc_sw_reset:1;	/* bit 6 */
-		u32 unused:24;		/* bits 7-30 */
-		u32 selfclr_disable:1;	/* bit 31 */
-#endif
-	} bits;
-} SW_RESET_t, *PSW_RESET_t;
 
 /*
- * structure for SLV Timer reg in global address map
- * located at address 0x002C
+ * SLV Timer reg at address 0x002C (low 24 bits)
  */
-typedef union _SLV_TIMER_t {
-	u32 value;
-	struct {
-#ifdef _BIT_FIELDS_HTOL
-		u32 unused:8;	/* bits 24-31 */
-		u32 timer_ini:24;	/* bits 0-23 */
-#else
-		u32 timer_ini:24;	/* bits 0-23 */
-		u32 unused:8;	/* bits 24-31 */
-#endif
-	} bits;
-} SLV_TIMER_t, *PSLV_TIMER_t;
 
 /*
  * structure for MSI Configuration reg in global address map
@@ -218,8 +186,8 @@ typedef struct _GLOBAL_t {			/* Location: */
 	u32 int_mask;				/*  0x001C */
 	u32 int_alias_clr_en;			/*  0x0020 */
 	u32 int_status_alias;			/*  0x0024 */
-	SW_RESET_t sw_reset;			/*  0x0028 */
-	SLV_TIMER_t slv_timer;			/*  0x002C */
+	u32 sw_reset;				/*  0x0028 */
+	u32 slv_timer;				/*  0x002C */
 	MSI_CONFIG_t msi_config;		/*  0x0030 */
 	LOOPBACK_t loopback;			/*  0x0034 */
 	u32 watchdog_timer;			/*  0x0038 */

drivers/staging/et131x/et131x_initpci.c

@@ -531,6 +531,76 @@ void et131x_link_detection_handler(unsigned long data)
 	}
 }
 
+/**
+ * et131x_configure_global_regs	-	configure JAGCore global regs
+ * @etdev: pointer to our adapter structure
+ *
+ * Used to configure the global registers on the JAGCore
+ */
+void ConfigGlobalRegs(struct et131x_adapter *etdev)
+{
+	struct _GLOBAL_t __iomem *pGbl = &etdev->regs->global;
+
+	DBG_ENTER(et131x_dbginfo);
+
+	if (etdev->RegistryPhyLoopbk == false) {
+		if (etdev->RegistryJumboPacket < 2048) {
+			/* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
+			 * block of RAM that the driver can split between Tx
+			 * and Rx as it desires.  Our default is to split it
+			 * 50/50:
+			 */
+			writel(0, &pGbl->rxq_start_addr);
+			writel(PARM_RX_MEM_END_DEF, &pGbl->rxq_end_addr);
+			writel(PARM_RX_MEM_END_DEF + 1, &pGbl->txq_start_addr);
+			writel(INTERNAL_MEM_SIZE - 1, &pGbl->txq_end_addr);
+		} else if (etdev->RegistryJumboPacket < 8192) {
+			/* For jumbo packets > 2k but < 8k, split 50-50. */
+			writel(0, &pGbl->rxq_start_addr);
+			writel(INTERNAL_MEM_RX_OFFSET, &pGbl->rxq_end_addr);
+			writel(INTERNAL_MEM_RX_OFFSET + 1, &pGbl->txq_start_addr);
+			writel(INTERNAL_MEM_SIZE - 1, &pGbl->txq_end_addr);
+		} else {
+			/* 9216 is the only packet size greater than 8k that
+			 * is available. The Tx buffer has to be big enough
+			 * for one whole packet on the Tx side. We'll make
+			 * the Tx 9408, and give the rest to Rx
+			 */
+			writel(0x0000, &pGbl->rxq_start_addr);
+			writel(0x01b3, &pGbl->rxq_end_addr);
+			writel(0x01b4, &pGbl->txq_start_addr);
+			writel(INTERNAL_MEM_SIZE - 1,&pGbl->txq_end_addr);
+		}
+
+		/* Initialize the loopback register. Disable all loopbacks. */
+		writel(0, &pGbl->loopback.value);
+	} else {
+		/* For PHY Line loopback, the memory is configured as if Tx
+		 * and Rx both have all the memory.  This is because the
+		 * RxMAC will write data into the space, and the TxMAC will
+		 * read it out.
+		 */
+		writel(0, &pGbl->rxq_start_addr);
+		writel(INTERNAL_MEM_SIZE - 1, &pGbl->rxq_end_addr);
+		writel(0, &pGbl->txq_start_addr);
+		writel(INTERNAL_MEM_SIZE - 1, &pGbl->txq_end_addr);
+
+		/* Initialize the loopback register (MAC loopback). */
+		writel(1, &pGbl->loopback);
+	}
+
+	/* MSI Register */
+	writel(0, &pGbl->msi_config.value);
+
+	/* By default, disable the watchdog timer.  It will be enabled when
+	 * a packet is queued.
+	 */
+	writel(0, &pGbl->watchdog_timer);
+
+	DBG_LEAVE(et131x_dbginfo);
+}
+
+
 /**
  * et131x_adapter_setup - Set the adapter up as per cassini+ documentation
  * @adapter: pointer to our private adapter structure
@@ -547,7 +617,10 @@ int et131x_adapter_setup(struct et131x_adapter *etdev)
 	ConfigGlobalRegs(etdev);
 
 	ConfigMACRegs1(etdev);
-	ConfigMMCRegs(etdev);
+
+	/* Configure the MMC registers */
+	/* All we need to do is initialize the Memory Control Register */
+	writel(ET_MMC_ENABLE, &etdev->regs->mmc.mmc_ctrl);
 
 	ConfigRxMacRegs(etdev);
 	ConfigTxMacRegs(etdev);
@@ -645,7 +718,7 @@ void et131x_soft_reset(struct et131x_adapter *adapter)
 	writel(0xc00f0000, &adapter->regs->mac.cfg1.value);
 
 	/* Set everything to a reset value */
-	writel(0x7F, &adapter->regs->global.sw_reset.value);
+	writel(0x7F, &adapter->regs->global.sw_reset);
 	writel(0x000f0000, &adapter->regs->mac.cfg1.value);
 	writel(0x00000000, &adapter->regs->mac.cfg1.value);