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drm/amd/display: Fix uninitialized variables in DC
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This fixes 49 UNINIT issues reported by Coverity.

Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Hung authored and Alex Deucher committed Apr 26, 2024
1 parent f95bcb0 commit ba3193f
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Showing 18 changed files with 39 additions and 39 deletions.
4 changes: 2 additions & 2 deletions drivers/gpu/drm/amd/display/dc/core/dc.c
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Expand Up @@ -1306,7 +1306,7 @@ static void disable_vbios_mode_if_required(

if (link != NULL && link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
unsigned int enc_inst, tg_inst = 0;
unsigned int pix_clk_100hz;
unsigned int pix_clk_100hz = 0;

enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
if (enc_inst != ENGINE_ID_UNKNOWN) {
Expand Down Expand Up @@ -1793,7 +1793,7 @@ bool dc_validate_boot_timing(const struct dc *dc,
return false;

if (dc_is_dp_signal(link->connector_signal)) {
unsigned int pix_clk_100hz;
unsigned int pix_clk_100hz = 0;
uint32_t numOdmPipes = 1;
uint32_t id_src[4] = {0};

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2 changes: 1 addition & 1 deletion drivers/gpu/drm/amd/display/dc/core/dc_resource.c
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Original file line number Diff line number Diff line change
Expand Up @@ -3042,7 +3042,7 @@ bool resource_update_pipes_for_plane_with_slice_count(
int i;
int dpp_pipe_count;
int cur_slice_count;
struct pipe_ctx *dpp_pipes[MAX_PIPES];
struct pipe_ctx *dpp_pipes[MAX_PIPES] = {0};
bool result = true;

dpp_pipe_count = resource_get_dpp_pipes_for_plane(plane,
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2 changes: 1 addition & 1 deletion drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
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Expand Up @@ -1183,7 +1183,7 @@ void mpc3_get_gamut_remap(struct mpc *mpc,
struct mpc_grph_gamut_adjustment *adjust)
{
struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
uint16_t arr_reg_val[12];
uint16_t arr_reg_val[12] = {0};
int select;

read_gamut_remap(mpc30, mpcc_id, arr_reg_val, &select);
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2 changes: 1 addition & 1 deletion drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
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Expand Up @@ -864,7 +864,7 @@ static unsigned int get_source_mpc_factor(const struct dml2_context *ctx,
struct dc_state *state,
const struct dc_plane_state *plane)
{
struct pipe_ctx *dpp_pipes[MAX_PIPES];
struct pipe_ctx *dpp_pipes[MAX_PIPES] = {0};
int dpp_pipe_count = ctx->config.callbacks.get_dpp_pipes_for_plane(plane,
&state->res_ctx, dpp_pipes);

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2 changes: 1 addition & 1 deletion drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
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Expand Up @@ -234,7 +234,7 @@ void dpp1_cm_get_gamut_remap(struct dpp *dpp_base,
struct dpp_grph_csc_adjustment *adjust)
{
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
uint16_t arr_reg_val[12];
uint16_t arr_reg_val[12] = {0};
enum gamut_remap_select select;

read_gamut_remap(dpp, arr_reg_val, &select);
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2 changes: 1 addition & 1 deletion drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
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Expand Up @@ -274,7 +274,7 @@ void dpp2_cm_get_gamut_remap(struct dpp *dpp_base,
struct dpp_grph_csc_adjustment *adjust)
{
struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
uint16_t arr_reg_val[12];
uint16_t arr_reg_val[12] = {0};
enum dcn20_gamut_remap_select select;

read_gamut_remap(dpp, arr_reg_val, &select);
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2 changes: 1 addition & 1 deletion drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
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Original file line number Diff line number Diff line change
Expand Up @@ -445,7 +445,7 @@ void dpp3_cm_get_gamut_remap(struct dpp *dpp_base,
struct dpp_grph_csc_adjustment *adjust)
{
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
uint16_t arr_reg_val[12];
uint16_t arr_reg_val[12] = {0};
int select;

read_gamut_remap(dpp, arr_reg_val, &select);
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6 changes: 3 additions & 3 deletions drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
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Original file line number Diff line number Diff line change
Expand Up @@ -128,7 +128,7 @@ struct gpio *dal_gpio_service_create_irq(
uint32_t offset,
uint32_t mask)
{
enum gpio_id id;
enum gpio_id id = 0;
uint32_t en;

if (!service->translate.funcs->offset_to_id(offset, mask, &id, &en)) {
Expand All @@ -144,7 +144,7 @@ struct gpio *dal_gpio_service_create_generic_mux(
uint32_t offset,
uint32_t mask)
{
enum gpio_id id;
enum gpio_id id = 0;
uint32_t en;
struct gpio *generic;

Expand Down Expand Up @@ -178,7 +178,7 @@ struct gpio_pin_info dal_gpio_get_generic_pin_info(
enum gpio_id id,
uint32_t en)
{
struct gpio_pin_info pin;
struct gpio_pin_info pin = {0};

if (service->translate.funcs->id_to_offset) {
service->translate.funcs->id_to_offset(id, en, &pin);
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4 changes: 2 additions & 2 deletions drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
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Expand Up @@ -1537,7 +1537,7 @@ enum dc_status dce110_apply_single_controller_ctx_to_hw(
}

if (pipe_ctx->stream_res.audio != NULL) {
struct audio_output audio_output;
struct audio_output audio_output = {0};

build_audio_output(context, pipe_ctx, &audio_output);

Expand Down Expand Up @@ -2260,7 +2260,7 @@ static void dce110_setup_audio_dto(
continue;

if (pipe_ctx->stream_res.audio != NULL) {
struct audio_output audio_output;
struct audio_output audio_output = {0};

build_audio_output(context, pipe_ctx, &audio_output);

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6 changes: 3 additions & 3 deletions drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
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Expand Up @@ -2185,7 +2185,7 @@ static int dcn10_align_pixel_clocks(struct dc *dc, int group_size,
struct dc_crtc_timing *hw_crtc_timing;
uint64_t phase[MAX_PIPES];
uint64_t modulo[MAX_PIPES];
unsigned int pclk;
unsigned int pclk = 0;

uint32_t embedded_pix_clk_100hz;
uint16_t embedded_h_total;
Expand Down Expand Up @@ -2276,7 +2276,7 @@ void dcn10_enable_vblanks_synchronization(
struct dc_context *dc_ctx = dc->ctx;
struct output_pixel_processor *opp;
struct timing_generator *tg;
int i, width, height, master;
int i, width = 0, height = 0, master;

DC_LOGGER_INIT(dc_ctx->logger);

Expand Down Expand Up @@ -2342,7 +2342,7 @@ void dcn10_enable_timing_synchronization(
struct dc_context *dc_ctx = dc->ctx;
struct output_pixel_processor *opp;
struct timing_generator *tg;
int i, width, height;
int i, width = 0, height = 0;

DC_LOGGER_INIT(dc_ctx->logger);

Expand Down
2 changes: 1 addition & 1 deletion drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
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Original file line number Diff line number Diff line change
Expand Up @@ -167,7 +167,7 @@ void dcn201_init_blank(
struct tg_color black_color = {0};
struct output_pixel_processor *opp = NULL;
uint32_t num_opps, opp_id_src0, opp_id_src1;
uint32_t otg_active_width, otg_active_height;
uint32_t otg_active_width = 0, otg_active_height = 0;

/* program opp dpg blank color */
color_space = COLOR_SPACE_SRGB;
Expand Down
2 changes: 1 addition & 1 deletion drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
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Original file line number Diff line number Diff line change
Expand Up @@ -66,7 +66,7 @@ static void mmhub_update_page_table_config(struct dcn_hubbub_phys_addr_config *c

int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
{
struct dcn_hubbub_phys_addr_config config;
struct dcn_hubbub_phys_addr_config config = {0};

config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
Expand Down
2 changes: 1 addition & 1 deletion drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
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Original file line number Diff line number Diff line change
Expand Up @@ -479,7 +479,7 @@ void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool p

int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
{
struct dcn_hubbub_phys_addr_config config;
struct dcn_hubbub_phys_addr_config config = {0};

config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
Expand Down
8 changes: 4 additions & 4 deletions drivers/gpu/drm/amd/display/dc/link/link_dpms.c
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Expand Up @@ -726,7 +726,7 @@ static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable)

static void enable_mst_on_sink(struct dc_link *link, bool enable)
{
unsigned char mstmCntl;
unsigned char mstmCntl = 0;

core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
if (enable)
Expand Down Expand Up @@ -804,7 +804,7 @@ void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)

if (enable) {
struct dsc_config dsc_cfg;
struct dsc_optc_config dsc_optc_cfg;
struct dsc_optc_config dsc_optc_cfg = {0};
enum optc_dsc_mode optc_dsc_mode;

/* Enable DSC hw block */
Expand Down Expand Up @@ -1576,7 +1576,7 @@ static bool write_128b_132b_sst_payload_allocation_table(
break;
}
} else {
union dpcd_rev dpcdRev;
union dpcd_rev dpcdRev = {0};

if (core_link_read_dpcd(
link,
Expand Down Expand Up @@ -2120,7 +2120,7 @@ static enum dc_status enable_link_dp_mst(
struct pipe_ctx *pipe_ctx)
{
struct dc_link *link = pipe_ctx->stream->link;
unsigned char mstm_cntl;
unsigned char mstm_cntl = 0;

/* sink signal type after MST branch is MST. Multiple MST sinks
* share one link. Link DP PHY is enable or training only once.
Expand Down
16 changes: 8 additions & 8 deletions drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
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Original file line number Diff line number Diff line change
Expand Up @@ -992,7 +992,7 @@ enum dp_link_encoding mst_decide_link_encoding_format(const struct dc_link *link

static void read_dp_device_vendor_id(struct dc_link *link)
{
struct dp_device_vendor_id dp_id;
struct dp_device_vendor_id dp_id = {0};

/* read IEEE branch device id */
core_link_read_dpcd(
Expand Down Expand Up @@ -1087,7 +1087,7 @@ static void get_active_converter_info(
}

if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
uint8_t det_caps[16] = {0}; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
union dwnstream_port_caps_byte0 *port_caps =
(union dwnstream_port_caps_byte0 *)det_caps;
if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
Expand Down Expand Up @@ -1172,7 +1172,7 @@ static void get_active_converter_info(
set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);

{
struct dp_sink_hw_fw_revision dp_hw_fw_revision;
struct dp_sink_hw_fw_revision dp_hw_fw_revision = {0};

core_link_read_dpcd(
link,
Expand Down Expand Up @@ -1242,7 +1242,7 @@ static void apply_usbc_combo_phy_reset_wa(struct dc_link *link,

bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
{
uint8_t dpcd_data[16];
uint8_t dpcd_data[16] = {0};
uint32_t read_dpcd_retry_cnt = 3;
enum dc_status status = DC_ERROR_UNEXPECTED;
union dp_downstream_port_present ds_port = { 0 };
Expand Down Expand Up @@ -1408,7 +1408,7 @@ static bool get_usbc_cable_id(struct dc_link *link, union dp_cable_id *cable_id)

static void retrieve_cable_id(struct dc_link *link)
{
union dp_cable_id usbc_cable_id;
union dp_cable_id usbc_cable_id = {0};

link->dpcd_caps.cable_id.raw = 0;
core_link_read_dpcd(link, DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX,
Expand Down Expand Up @@ -1475,7 +1475,7 @@ static bool dpcd_read_sink_ext_caps(struct dc_link *link)

enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link)
{
uint8_t lttpr_dpcd_data[8];
uint8_t lttpr_dpcd_data[8] = {0};
enum dc_status status;
bool is_lttpr_present;

Expand Down Expand Up @@ -1931,8 +1931,8 @@ void detect_edp_sink_caps(struct dc_link *link)
uint32_t entry;
uint32_t link_rate_in_khz;
enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
uint8_t backlight_adj_cap;
uint8_t general_edp_cap;
uint8_t backlight_adj_cap = 0;
uint8_t general_edp_cap = 0;

retrieve_link_cap(link);
link->dpcd_caps.edp_supported_link_rates_count = 0;
Expand Down
10 changes: 5 additions & 5 deletions drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
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Original file line number Diff line number Diff line change
Expand Up @@ -120,7 +120,7 @@ bool dp_parse_link_loss_status(

static bool handle_hpd_irq_psr_sink(struct dc_link *link)
{
union dpcd_psr_configuration psr_configuration;
union dpcd_psr_configuration psr_configuration = {0};

if (!link->psr_settings.psr_feature_enabled)
return false;
Expand Down Expand Up @@ -186,9 +186,9 @@ static bool handle_hpd_irq_psr_sink(struct dc_link *link)

static void handle_hpd_irq_replay_sink(struct dc_link *link)
{
union dpcd_replay_configuration replay_configuration;
union dpcd_replay_configuration replay_configuration = {0};
/*AMD Replay version reuse DP_PSR_ERROR_STATUS for REPLAY_ERROR status.*/
union psr_error_status replay_error_status;
union psr_error_status replay_error_status = {0};

if (!link->replay_settings.replay_feature_enabled)
return;
Expand Down Expand Up @@ -280,7 +280,7 @@ void dp_handle_link_loss(struct dc_link *link)
static void read_dpcd204h_on_irq_hpd(struct dc_link *link, union hpd_irq_data *irq_data)
{
enum dc_status retval;
union lane_align_status_updated dpcd_lane_status_updated;
union lane_align_status_updated dpcd_lane_status_updated = {0};

retval = core_link_read_dpcd(
link,
Expand Down Expand Up @@ -320,7 +320,7 @@ enum dc_status dp_read_hpd_rx_irq_data(
/* Read 14 bytes in a single read and then copy only the required fields.
* This is more efficient than doing it in two separate AUX reads. */

uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1] = {0};

retval = core_link_read_dpcd(
link,
Expand Down
4 changes: 2 additions & 2 deletions drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
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Original file line number Diff line number Diff line change
Expand Up @@ -321,8 +321,8 @@ bool edp_is_ilr_optimization_required(struct dc_link *link,
struct dc_crtc_timing *crtc_timing)
{
struct dc_link_settings link_setting;
uint8_t link_bw_set;
uint8_t link_rate_set;
uint8_t link_bw_set = 0;
uint8_t link_rate_set = 0;
uint32_t req_bw;
union lane_count_set lane_count_set = {0};

Expand Down
2 changes: 1 addition & 1 deletion drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.c
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Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,7 @@

bool link_get_hpd_state(struct dc_link *link)
{
uint32_t state;
uint32_t state = 0;

dal_gpio_lock_pin(link->hpd_gpio);
dal_gpio_get_value(link->hpd_gpio, &state);
Expand Down

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