Skip to content

Commit

Permalink
clk: meson: mpll: Delete a useless spinlock from the MPLL
Browse files Browse the repository at this point in the history 
The register corresponding to MPLL does not share the same register
with other module drivers, so there is no concurrent access to the
register with other modules drivers. The spinlock defined in struct
meson_clk_mpll_data is no longer useful.

Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20240925-mpll_spinlock-v2-1-8f9b73588ec1@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
  • Loading branch information
Chuan Liu authored and Jerome Brunet committed Sep 30, 2024
1 parent 5e052ef commit bbf7e40
Show file tree
Hide file tree
Showing 7 changed files with 0 additions and 39 deletions.
6 changes: 0 additions & 6 deletions drivers/clk/meson/axg.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -23,8 +23,6 @@

#include <dt-bindings/clock/axg-clkc.h>

static DEFINE_SPINLOCK(meson_clk_lock);

static struct clk_regmap axg_fixed_pll_dco = {
.data = &(struct meson_clk_pll_data){
.en = {
Expand Down Expand Up @@ -506,7 +504,6 @@ static struct clk_regmap axg_mpll0_div = {
.shift = 0,
.width = 1,
},
.lock = &meson_clk_lock,
.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
Expand Down Expand Up @@ -557,7 +554,6 @@ static struct clk_regmap axg_mpll1_div = {
.shift = 1,
.width = 1,
},
.lock = &meson_clk_lock,
.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
Expand Down Expand Up @@ -613,7 +609,6 @@ static struct clk_regmap axg_mpll2_div = {
.shift = 2,
.width = 1,
},
.lock = &meson_clk_lock,
.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
Expand Down Expand Up @@ -664,7 +659,6 @@ static struct clk_regmap axg_mpll3_div = {
.shift = 3,
.width = 1,
},
.lock = &meson_clk_lock,
.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
Expand Down
11 changes: 0 additions & 11 deletions drivers/clk/meson/clk-mpll.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -112,26 +112,15 @@ static int mpll_set_rate(struct clk_hw *hw,
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
unsigned int sdm, n2;
unsigned long flags = 0;

params_from_rate(rate, parent_rate, &sdm, &n2, mpll->flags);

if (mpll->lock)
spin_lock_irqsave(mpll->lock, flags);
else
__acquire(mpll->lock);

/* Set the fractional part */
meson_parm_write(clk->map, &mpll->sdm, sdm);

/* Set the integer divider part */
meson_parm_write(clk->map, &mpll->n2, n2);

if (mpll->lock)
spin_unlock_irqrestore(mpll->lock, flags);
else
__release(mpll->lock);

return 0;
}

Expand Down
1 change: 0 additions & 1 deletion drivers/clk/meson/clk-mpll.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,6 @@ struct meson_clk_mpll_data {
struct parm misc;
const struct reg_sequence *init_regs;
unsigned int init_count;
spinlock_t *lock;
u8 flags;
};

Expand Down
6 changes: 0 additions & 6 deletions drivers/clk/meson/g12a.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -28,8 +28,6 @@

#include <dt-bindings/clock/g12a-clkc.h>

static DEFINE_SPINLOCK(meson_clk_lock);

static struct clk_regmap g12a_fixed_pll_dco = {
.data = &(struct meson_clk_pll_data){
.en = {
Expand Down Expand Up @@ -2225,7 +2223,6 @@ static struct clk_regmap g12a_mpll0_div = {
.shift = 29,
.width = 1,
},
.lock = &meson_clk_lock,
.init_regs = g12a_mpll0_init_regs,
.init_count = ARRAY_SIZE(g12a_mpll0_init_regs),
},
Expand Down Expand Up @@ -2279,7 +2276,6 @@ static struct clk_regmap g12a_mpll1_div = {
.shift = 29,
.width = 1,
},
.lock = &meson_clk_lock,
.init_regs = g12a_mpll1_init_regs,
.init_count = ARRAY_SIZE(g12a_mpll1_init_regs),
},
Expand Down Expand Up @@ -2333,7 +2329,6 @@ static struct clk_regmap g12a_mpll2_div = {
.shift = 29,
.width = 1,
},
.lock = &meson_clk_lock,
.init_regs = g12a_mpll2_init_regs,
.init_count = ARRAY_SIZE(g12a_mpll2_init_regs),
},
Expand Down Expand Up @@ -2387,7 +2382,6 @@ static struct clk_regmap g12a_mpll3_div = {
.shift = 29,
.width = 1,
},
.lock = &meson_clk_lock,
.init_regs = g12a_mpll3_init_regs,
.init_count = ARRAY_SIZE(g12a_mpll3_init_regs),
},
Expand Down
6 changes: 0 additions & 6 deletions drivers/clk/meson/gxbb.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -19,8 +19,6 @@

#include <dt-bindings/clock/gxbb-clkc.h>

static DEFINE_SPINLOCK(meson_clk_lock);

static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
PLL_PARAMS(32, 1),
PLL_PARAMS(33, 1),
Expand Down Expand Up @@ -731,7 +729,6 @@ static struct clk_regmap gxbb_mpll0_div = {
.shift = 16,
.width = 9,
},
.lock = &meson_clk_lock,
},
.hw.init = &(struct clk_init_data){
.name = "mpll0_div",
Expand Down Expand Up @@ -760,7 +757,6 @@ static struct clk_regmap gxl_mpll0_div = {
.shift = 16,
.width = 9,
},
.lock = &meson_clk_lock,
},
.hw.init = &(struct clk_init_data){
.name = "mpll0_div",
Expand Down Expand Up @@ -812,7 +808,6 @@ static struct clk_regmap gxbb_mpll1_div = {
.shift = 16,
.width = 9,
},
.lock = &meson_clk_lock,
},
.hw.init = &(struct clk_init_data){
.name = "mpll1_div",
Expand Down Expand Up @@ -855,7 +850,6 @@ static struct clk_regmap gxbb_mpll2_div = {
.shift = 16,
.width = 9,
},
.lock = &meson_clk_lock,
},
.hw.init = &(struct clk_init_data){
.name = "mpll2_div",
Expand Down
3 changes: 0 additions & 3 deletions drivers/clk/meson/meson8b.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -492,7 +492,6 @@ static struct clk_regmap meson8b_mpll0_div = {
.shift = 25,
.width = 1,
},
.lock = &meson_clk_lock,
},
.hw.init = &(struct clk_init_data){
.name = "mpll0_div",
Expand Down Expand Up @@ -537,7 +536,6 @@ static struct clk_regmap meson8b_mpll1_div = {
.shift = 16,
.width = 9,
},
.lock = &meson_clk_lock,
},
.hw.init = &(struct clk_init_data){
.name = "mpll1_div",
Expand Down Expand Up @@ -582,7 +580,6 @@ static struct clk_regmap meson8b_mpll2_div = {
.shift = 16,
.width = 9,
},
.lock = &meson_clk_lock,
},
.hw.init = &(struct clk_init_data){
.name = "mpll2_div",
Expand Down
6 changes: 0 additions & 6 deletions drivers/clk/meson/s4-pll.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,8 +17,6 @@
#include "meson-clkc-utils.h"
#include <dt-bindings/clock/amlogic,s4-pll-clkc.h>

static DEFINE_SPINLOCK(meson_clk_lock);

/*
* These clock are a fixed value (fixed_pll is 2GHz) that is initialized by ROMcode.
* The chip was changed fixed pll for security reasons. Fixed PLL registers are not writable
Expand Down Expand Up @@ -547,7 +545,6 @@ static struct clk_regmap s4_mpll0_div = {
.shift = 29,
.width = 1,
},
.lock = &meson_clk_lock,
.init_regs = s4_mpll0_init_regs,
.init_count = ARRAY_SIZE(s4_mpll0_init_regs),
},
Expand Down Expand Up @@ -601,7 +598,6 @@ static struct clk_regmap s4_mpll1_div = {
.shift = 29,
.width = 1,
},
.lock = &meson_clk_lock,
.init_regs = s4_mpll1_init_regs,
.init_count = ARRAY_SIZE(s4_mpll1_init_regs),
},
Expand Down Expand Up @@ -655,7 +651,6 @@ static struct clk_regmap s4_mpll2_div = {
.shift = 29,
.width = 1,
},
.lock = &meson_clk_lock,
.init_regs = s4_mpll2_init_regs,
.init_count = ARRAY_SIZE(s4_mpll2_init_regs),
},
Expand Down Expand Up @@ -709,7 +704,6 @@ static struct clk_regmap s4_mpll3_div = {
.shift = 29,
.width = 1,
},
.lock = &meson_clk_lock,
.init_regs = s4_mpll3_init_regs,
.init_count = ARRAY_SIZE(s4_mpll3_init_regs),
},
Expand Down

0 comments on commit bbf7e40

Please sign in to comment.