Revert "Merge branch 'wwan-t7xx-fw-flashing-and-coredump-support'"

This reverts commit 5417197, reversing
changes made to 0630f64.

Reverting to allow addressing review comments.

Link: https://lore.kernel.org/all/4c5dbea0-52a9-1c3d-7547-00ea54c90550@linux.intel.com/
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

Documentation/networking/devlink/index.rst

@@ -67,4 +67,3 @@ parameters, info versions, and other features it supports.
    prestera
    iosm
    octeontx2
-   t7xx

drivers/net/wwan/Kconfig

@@ -108,7 +108,6 @@ config IOSM
 config MTK_T7XX
 	tristate "MediaTek PCIe 5G WWAN modem T7xx device"
 	depends on PCI
-	select NET_DEVLINK
 	help
 	  Enables MediaTek PCIe based 5G WWAN modem (T7xx series) device.
 	  Adapts WWAN framework and provides network interface like wwan0

drivers/net/wwan/t7xx/Makefile

@@ -17,7 +17,4 @@ mtk_t7xx-y:=	t7xx_pci.o \
 		t7xx_hif_dpmaif_tx.o \
 		t7xx_hif_dpmaif_rx.o  \
 		t7xx_dpmaif.o \
-		t7xx_netdev.o \
-		t7xx_pci_rescan.o \
-		t7xx_uevent.o \
-		t7xx_port_devlink.o
+		t7xx_netdev.o

drivers/net/wwan/t7xx/t7xx_hif_cldma.c

@@ -57,6 +57,8 @@
 #define CHECK_Q_STOP_TIMEOUT_US		1000000
 #define CHECK_Q_STOP_STEP_US		10000
 
+#define CLDMA_JUMBO_BUFF_SZ		(63 * 1024 + sizeof(struct ccci_header))
+
 static void md_cd_queue_struct_reset(struct cldma_queue *queue, struct cldma_ctrl *md_ctrl,
 				     enum mtk_txrx tx_rx, unsigned int index)
 {
@@ -991,34 +993,6 @@ int t7xx_cldma_send_skb(struct cldma_ctrl *md_ctrl, int qno, struct sk_buff *skb
 	return ret;
 }
 
-static void t7xx_cldma_adjust_config(struct cldma_ctrl *md_ctrl, enum cldma_cfg cfg_id)
-{
-	int qno;
-
-	for (qno = 0; qno < CLDMA_RXQ_NUM; qno++) {
-		md_ctrl->rx_ring[qno].pkt_size = CLDMA_SHARED_Q_BUFF_SZ;
-		md_ctrl->rxq[qno].q_type = CLDMA_SHARED_Q;
-	}
-
-	md_ctrl->rx_ring[CLDMA_RXQ_NUM - 1].pkt_size = CLDMA_JUMBO_BUFF_SZ;
-
-	for (qno = 0; qno < CLDMA_TXQ_NUM; qno++) {
-		md_ctrl->tx_ring[qno].pkt_size = CLDMA_SHARED_Q_BUFF_SZ;
-		md_ctrl->txq[qno].q_type = CLDMA_SHARED_Q;
-	}
-
-	if (cfg_id == CLDMA_DEDICATED_Q_CFG) {
-		md_ctrl->rxq[DOWNLOAD_PORT_ID].q_type = CLDMA_DEDICATED_Q;
-		md_ctrl->txq[DOWNLOAD_PORT_ID].q_type = CLDMA_DEDICATED_Q;
-		md_ctrl->tx_ring[DOWNLOAD_PORT_ID].pkt_size = CLDMA_DEDICATED_Q_BUFF_SZ;
-		md_ctrl->rx_ring[DOWNLOAD_PORT_ID].pkt_size = CLDMA_DEDICATED_Q_BUFF_SZ;
-		md_ctrl->rxq[DUMP_PORT_ID].q_type = CLDMA_DEDICATED_Q;
-		md_ctrl->txq[DUMP_PORT_ID].q_type = CLDMA_DEDICATED_Q;
-		md_ctrl->tx_ring[DUMP_PORT_ID].pkt_size = CLDMA_DEDICATED_Q_BUFF_SZ;
-		md_ctrl->rx_ring[DUMP_PORT_ID].pkt_size = CLDMA_DEDICATED_Q_BUFF_SZ;
-	}
-}
-
 static int t7xx_cldma_late_init(struct cldma_ctrl *md_ctrl)
 {
 	char dma_pool_name[32];
@@ -1047,6 +1021,11 @@ static int t7xx_cldma_late_init(struct cldma_ctrl *md_ctrl)
 	}
 
 	for (j = 0; j < CLDMA_RXQ_NUM; j++) {
+		md_ctrl->rx_ring[j].pkt_size = CLDMA_MTU;
+
+		if (j == CLDMA_RXQ_NUM - 1)
+			md_ctrl->rx_ring[j].pkt_size = CLDMA_JUMBO_BUFF_SZ;
+
 		ret = t7xx_cldma_rx_ring_init(md_ctrl, &md_ctrl->rx_ring[j]);
 		if (ret) {
 			dev_err(md_ctrl->dev, "Control RX ring init fail\n");
@@ -1085,18 +1064,13 @@ static void t7xx_hw_info_init(struct cldma_ctrl *md_ctrl)
 	struct t7xx_cldma_hw *hw_info = &md_ctrl->hw_info;
 	u32 phy_ao_base, phy_pd_base;
 
-	hw_info->hw_mode = MODE_BIT_64;
-
-	if (md_ctrl->hif_id == CLDMA_ID_MD) {
-		phy_ao_base = CLDMA1_AO_BASE;
-		phy_pd_base = CLDMA1_PD_BASE;
-		hw_info->phy_interrupt_id = CLDMA1_INT;
-	} else {
-		phy_ao_base = CLDMA0_AO_BASE;
-		phy_pd_base = CLDMA0_PD_BASE;
-		hw_info->phy_interrupt_id = CLDMA0_INT;
-	}
+	if (md_ctrl->hif_id != CLDMA_ID_MD)
+		return;
 
+	phy_ao_base = CLDMA1_AO_BASE;
+	phy_pd_base = CLDMA1_PD_BASE;
+	hw_info->phy_interrupt_id = CLDMA1_INT;
+	hw_info->hw_mode = MODE_BIT_64;
 	hw_info->ap_ao_base = t7xx_pcie_addr_transfer(pbase->pcie_ext_reg_base,
 						      pbase->pcie_dev_reg_trsl_addr, phy_ao_base);
 	hw_info->ap_pdn_base = t7xx_pcie_addr_transfer(pbase->pcie_ext_reg_base,
@@ -1350,10 +1324,9 @@ int t7xx_cldma_init(struct cldma_ctrl *md_ctrl)
 	return -ENOMEM;
 }
 
-void t7xx_cldma_switch_cfg(struct cldma_ctrl *md_ctrl, enum cldma_cfg cfg_id)
+void t7xx_cldma_switch_cfg(struct cldma_ctrl *md_ctrl)
 {
 	t7xx_cldma_late_release(md_ctrl);
-	t7xx_cldma_adjust_config(md_ctrl, cfg_id);
 	t7xx_cldma_late_init(md_ctrl);
 }
 

drivers/net/wwan/t7xx/t7xx_hif_cldma.h

@@ -31,14 +31,10 @@
 #include "t7xx_cldma.h"
 #include "t7xx_pci.h"
 
-#define CLDMA_JUMBO_BUFF_SZ		(63 * 1024 + sizeof(struct ccci_header))
-#define CLDMA_SHARED_Q_BUFF_SZ		3584
-#define CLDMA_DEDICATED_Q_BUFF_SZ	2048
-
 /**
  * enum cldma_id - Identifiers for CLDMA HW units.
  * @CLDMA_ID_MD: Modem control channel.
- * @CLDMA_ID_AP: Application Processor control channel.
+ * @CLDMA_ID_AP: Application Processor control channel (not used at the moment).
  * @CLDMA_NUM:   Number of CLDMA HW units available.
  */
 enum cldma_id {
@@ -59,16 +55,6 @@ struct cldma_gpd {
 	__le16 not_used2;
 };
 
-enum cldma_queue_type {
-	CLDMA_SHARED_Q,
-	CLDMA_DEDICATED_Q,
-};
-
-enum cldma_cfg {
-	CLDMA_SHARED_Q_CFG,
-	CLDMA_DEDICATED_Q_CFG,
-};
-
 struct cldma_request {
 	struct cldma_gpd *gpd;	/* Virtual address for CPU */
 	dma_addr_t gpd_addr;	/* Physical address for DMA */
@@ -91,7 +77,6 @@ struct cldma_queue {
 	struct cldma_request *tr_done;
 	struct cldma_request *rx_refill;
 	struct cldma_request *tx_next;
-	enum cldma_queue_type q_type;
 	int budget;			/* Same as ring buffer size by default */
 	spinlock_t ring_lock;
 	wait_queue_head_t req_wq;	/* Only for TX */
@@ -119,20 +104,17 @@ struct cldma_ctrl {
 	int (*recv_skb)(struct cldma_queue *queue, struct sk_buff *skb);
 };
 
-enum cldma_txq_rxq_port_id {
-	DOWNLOAD_PORT_ID = 0,
-	DUMP_PORT_ID = 1
-};
-
 #define GPD_FLAGS_HWO		BIT(0)
 #define GPD_FLAGS_IOC		BIT(7)
 #define GPD_DMAPOOL_ALIGN	16
 
+#define CLDMA_MTU		3584	/* 3.5kB */
+
 int t7xx_cldma_alloc(enum cldma_id hif_id, struct t7xx_pci_dev *t7xx_dev);
 void t7xx_cldma_hif_hw_init(struct cldma_ctrl *md_ctrl);
 int t7xx_cldma_init(struct cldma_ctrl *md_ctrl);
 void t7xx_cldma_exit(struct cldma_ctrl *md_ctrl);
-void t7xx_cldma_switch_cfg(struct cldma_ctrl *md_ctrl, enum cldma_cfg cfg_id);
+void t7xx_cldma_switch_cfg(struct cldma_ctrl *md_ctrl);
 void t7xx_cldma_start(struct cldma_ctrl *md_ctrl);
 int t7xx_cldma_stop(struct cldma_ctrl *md_ctrl);
 void t7xx_cldma_reset(struct cldma_ctrl *md_ctrl);

drivers/net/wwan/t7xx/t7xx_mhccif.h

@@ -25,7 +25,6 @@
 			 D2H_INT_EXCEPTION_CLEARQ_DONE |	\
 			 D2H_INT_EXCEPTION_ALLQ_RESET |		\
 			 D2H_INT_PORT_ENUM |			\
-			 D2H_INT_ASYNC_AP_HK |			\
 			 D2H_INT_ASYNC_MD_HK)
 
 void t7xx_mhccif_mask_set(struct t7xx_pci_dev *t7xx_dev, u32 val);