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Revert "drm/i915/tgl: Add extra hdc flush workaround"
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This reverts commit 36a6b5d.

The commit takes care Wa_1604544889 which was fixed on a0 stepping based on
a0 replan. So no SW workaround is required on any stepping now.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Fixes: 36a6b5d ("drm/i915/tgl: Add extra hdc flush workaround")
Link: https://patchwork.freedesktop.org/patch/msgid/1c751032ce79c80c5485cae315f1a9904ce07cac.1583359940.git.caz.yokoyama@intel.com
(cherry picked from commit 175c4d9)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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Caz Yokoyama authored and Jani Nikula committed Mar 16, 2020
1 parent 9777d8b commit c09f6b4
Showing 1 changed file with 0 additions and 20 deletions.
20 changes: 0 additions & 20 deletions drivers/gpu/drm/i915/gt/intel_lrc.c
Original file line number Diff line number Diff line change
Expand Up @@ -4000,26 +4000,6 @@ static int gen12_emit_flush_render(struct i915_request *request,

*cs++ = preparser_disable(false);
intel_ring_advance(request, cs);

/*
* Wa_1604544889:tgl
*/
if (IS_TGL_REVID(request->i915, TGL_REVID_A0, TGL_REVID_A0)) {
flags = 0;
flags |= PIPE_CONTROL_CS_STALL;
flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;

flags |= PIPE_CONTROL_STORE_DATA_INDEX;
flags |= PIPE_CONTROL_QW_WRITE;

cs = intel_ring_begin(request, 6);
if (IS_ERR(cs))
return PTR_ERR(cs);

cs = gen8_emit_pipe_control(cs, flags,
LRC_PPHWSP_SCRATCH_ADDR);
intel_ring_advance(request, cs);
}
}

return 0;
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