-
Notifications
You must be signed in to change notification settings - Fork 0
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
net: ti: icssg-prueth: Add ICSSG Stats
Add icssg_stats.c to help dump, icssg related driver statistics. ICSSG has hardware registers for providing statistics like total rx bytes, total tx bytes, etc. These registers are of 32 bits and hence in case of 1G link, they overflows in around 32 seconds. The behaviour of these registers is such that they don't roll back to 0 after overflow but rather stay at UINT_MAX. These registers support a feature where the value written to them is subtracted from the register. This feature can be utilized to fix the overflowing of stats. This solution uses a Workqueues based solution where a function gets called before the registers overflow (every 25 seconds in 1G link, 25000 seconds in 100M link), this function saves the register values in local variables and writes the last read value to the register. So any update during the read will be taken care of. Signed-off-by: MD Danish Anwar <danishanwar@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
- Loading branch information
MD Danish Anwar
authored and
David S. Miller
committed
Aug 2, 2023
1 parent
128d587
commit c1e10d5
Showing
5 changed files
with
219 additions
and
0 deletions.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,44 @@ | ||
// SPDX-License-Identifier: GPL-2.0 | ||
/* Texas Instruments ICSSG Ethernet driver | ||
* | ||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ | ||
* | ||
*/ | ||
|
||
#include "icssg_prueth.h" | ||
#include "icssg_stats.h" | ||
#include <linux/regmap.h> | ||
|
||
static u32 stats_base[] = { 0x54c, /* Slice 0 stats start */ | ||
0xb18, /* Slice 1 stats start */ | ||
}; | ||
|
||
void emac_update_hardware_stats(struct prueth_emac *emac) | ||
{ | ||
struct prueth *prueth = emac->prueth; | ||
int slice = prueth_emac_slice(emac); | ||
u32 base = stats_base[slice]; | ||
u32 val; | ||
int i; | ||
|
||
for (i = 0; i < ARRAY_SIZE(icssg_all_stats); i++) { | ||
regmap_read(prueth->miig_rt, | ||
base + icssg_all_stats[i].offset, | ||
&val); | ||
regmap_write(prueth->miig_rt, | ||
base + icssg_all_stats[i].offset, | ||
val); | ||
|
||
emac->stats[i] += val; | ||
} | ||
} | ||
|
||
void emac_stats_work_handler(struct work_struct *work) | ||
{ | ||
struct prueth_emac *emac = container_of(work, struct prueth_emac, | ||
stats_work.work); | ||
emac_update_hardware_stats(emac); | ||
|
||
queue_delayed_work(system_long_wq, &emac->stats_work, | ||
msecs_to_jiffies((STATS_TIME_LIMIT_1G_MS * 1000) / emac->speed)); | ||
} |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,158 @@ | ||
/* SPDX-License-Identifier: GPL-2.0 */ | ||
/* Texas Instruments ICSSG Ethernet driver | ||
* | ||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ | ||
* | ||
*/ | ||
|
||
#ifndef __NET_TI_ICSSG_STATS_H | ||
#define __NET_TI_ICSSG_STATS_H | ||
|
||
#include "icssg_prueth.h" | ||
|
||
#define STATS_TIME_LIMIT_1G_MS 25000 /* 25 seconds @ 1G */ | ||
|
||
struct miig_stats_regs { | ||
/* Rx */ | ||
u32 rx_packets; | ||
u32 rx_broadcast_frames; | ||
u32 rx_multicast_frames; | ||
u32 rx_crc_errors; | ||
u32 rx_mii_error_frames; | ||
u32 rx_odd_nibble_frames; | ||
u32 rx_frame_max_size; | ||
u32 rx_max_size_error_frames; | ||
u32 rx_frame_min_size; | ||
u32 rx_min_size_error_frames; | ||
u32 rx_over_errors; | ||
u32 rx_class0_hits; | ||
u32 rx_class1_hits; | ||
u32 rx_class2_hits; | ||
u32 rx_class3_hits; | ||
u32 rx_class4_hits; | ||
u32 rx_class5_hits; | ||
u32 rx_class6_hits; | ||
u32 rx_class7_hits; | ||
u32 rx_class8_hits; | ||
u32 rx_class9_hits; | ||
u32 rx_class10_hits; | ||
u32 rx_class11_hits; | ||
u32 rx_class12_hits; | ||
u32 rx_class13_hits; | ||
u32 rx_class14_hits; | ||
u32 rx_class15_hits; | ||
u32 rx_smd_frags; | ||
u32 rx_bucket1_size; | ||
u32 rx_bucket2_size; | ||
u32 rx_bucket3_size; | ||
u32 rx_bucket4_size; | ||
u32 rx_64B_frames; | ||
u32 rx_bucket1_frames; | ||
u32 rx_bucket2_frames; | ||
u32 rx_bucket3_frames; | ||
u32 rx_bucket4_frames; | ||
u32 rx_bucket5_frames; | ||
u32 rx_bytes; | ||
u32 rx_tx_total_bytes; | ||
/* Tx */ | ||
u32 tx_packets; | ||
u32 tx_broadcast_frames; | ||
u32 tx_multicast_frames; | ||
u32 tx_odd_nibble_frames; | ||
u32 tx_underflow_errors; | ||
u32 tx_frame_max_size; | ||
u32 tx_max_size_error_frames; | ||
u32 tx_frame_min_size; | ||
u32 tx_min_size_error_frames; | ||
u32 tx_bucket1_size; | ||
u32 tx_bucket2_size; | ||
u32 tx_bucket3_size; | ||
u32 tx_bucket4_size; | ||
u32 tx_64B_frames; | ||
u32 tx_bucket1_frames; | ||
u32 tx_bucket2_frames; | ||
u32 tx_bucket3_frames; | ||
u32 tx_bucket4_frames; | ||
u32 tx_bucket5_frames; | ||
u32 tx_bytes; | ||
}; | ||
|
||
#define ICSSG_STATS(field, stats_type) \ | ||
{ \ | ||
#field, \ | ||
offsetof(struct miig_stats_regs, field), \ | ||
stats_type \ | ||
} | ||
|
||
struct icssg_stats { | ||
char name[ETH_GSTRING_LEN]; | ||
u32 offset; | ||
bool standard_stats; | ||
}; | ||
|
||
static const struct icssg_stats icssg_all_stats[] = { | ||
/* Rx */ | ||
ICSSG_STATS(rx_packets, true), | ||
ICSSG_STATS(rx_broadcast_frames, false), | ||
ICSSG_STATS(rx_multicast_frames, true), | ||
ICSSG_STATS(rx_crc_errors, true), | ||
ICSSG_STATS(rx_mii_error_frames, false), | ||
ICSSG_STATS(rx_odd_nibble_frames, false), | ||
ICSSG_STATS(rx_frame_max_size, true), | ||
ICSSG_STATS(rx_max_size_error_frames, false), | ||
ICSSG_STATS(rx_frame_min_size, true), | ||
ICSSG_STATS(rx_min_size_error_frames, false), | ||
ICSSG_STATS(rx_over_errors, true), | ||
ICSSG_STATS(rx_class0_hits, false), | ||
ICSSG_STATS(rx_class1_hits, false), | ||
ICSSG_STATS(rx_class2_hits, false), | ||
ICSSG_STATS(rx_class3_hits, false), | ||
ICSSG_STATS(rx_class4_hits, false), | ||
ICSSG_STATS(rx_class5_hits, false), | ||
ICSSG_STATS(rx_class6_hits, false), | ||
ICSSG_STATS(rx_class7_hits, false), | ||
ICSSG_STATS(rx_class8_hits, false), | ||
ICSSG_STATS(rx_class9_hits, false), | ||
ICSSG_STATS(rx_class10_hits, false), | ||
ICSSG_STATS(rx_class11_hits, false), | ||
ICSSG_STATS(rx_class12_hits, false), | ||
ICSSG_STATS(rx_class13_hits, false), | ||
ICSSG_STATS(rx_class14_hits, false), | ||
ICSSG_STATS(rx_class15_hits, false), | ||
ICSSG_STATS(rx_smd_frags, false), | ||
ICSSG_STATS(rx_bucket1_size, true), | ||
ICSSG_STATS(rx_bucket2_size, true), | ||
ICSSG_STATS(rx_bucket3_size, true), | ||
ICSSG_STATS(rx_bucket4_size, true), | ||
ICSSG_STATS(rx_64B_frames, true), | ||
ICSSG_STATS(rx_bucket1_frames, true), | ||
ICSSG_STATS(rx_bucket2_frames, true), | ||
ICSSG_STATS(rx_bucket3_frames, true), | ||
ICSSG_STATS(rx_bucket4_frames, true), | ||
ICSSG_STATS(rx_bucket5_frames, true), | ||
ICSSG_STATS(rx_bytes, true), | ||
ICSSG_STATS(rx_tx_total_bytes, false), | ||
/* Tx */ | ||
ICSSG_STATS(tx_packets, true), | ||
ICSSG_STATS(tx_broadcast_frames, false), | ||
ICSSG_STATS(tx_multicast_frames, false), | ||
ICSSG_STATS(tx_odd_nibble_frames, false), | ||
ICSSG_STATS(tx_underflow_errors, false), | ||
ICSSG_STATS(tx_frame_max_size, true), | ||
ICSSG_STATS(tx_max_size_error_frames, false), | ||
ICSSG_STATS(tx_frame_min_size, true), | ||
ICSSG_STATS(tx_min_size_error_frames, false), | ||
ICSSG_STATS(tx_bucket1_size, true), | ||
ICSSG_STATS(tx_bucket2_size, true), | ||
ICSSG_STATS(tx_bucket3_size, true), | ||
ICSSG_STATS(tx_bucket4_size, true), | ||
ICSSG_STATS(tx_64B_frames, true), | ||
ICSSG_STATS(tx_bucket1_frames, true), | ||
ICSSG_STATS(tx_bucket2_frames, true), | ||
ICSSG_STATS(tx_bucket3_frames, true), | ||
ICSSG_STATS(tx_bucket4_frames, true), | ||
ICSSG_STATS(tx_bucket5_frames, true), | ||
ICSSG_STATS(tx_bytes, true), | ||
}; | ||
|
||
#endif /* __NET_TI_ICSSG_STATS_H */ |