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drm/amdkfd: replace kgd_dev in static gfx v10_3 funcs
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Static funcs in amdgpu_amdkfd_gfx_v10_3.c now using amdgpu_device.

Signed-off-by: Graham Sider <Graham.Sider@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Graham Sider authored and Alex Deucher committed Nov 17, 2021
1 parent 4056b03 commit c531a58
Showing 1 changed file with 23 additions and 29 deletions.
52 changes: 23 additions & 29 deletions drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
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Original file line number Diff line number Diff line change
Expand Up @@ -43,32 +43,26 @@ static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
return (struct amdgpu_device *)kgd;
}

static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,
uint32_t queue, uint32_t vmid)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);

mutex_lock(&adev->srbm_mutex);
nv_grbm_select(adev, mec, pipe, queue, vmid);
}

static void unlock_srbm(struct kgd_dev *kgd)
static void unlock_srbm(struct amdgpu_device *adev)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);

nv_grbm_select(adev, 0, 0, 0, 0);
mutex_unlock(&adev->srbm_mutex);
}

static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
static void acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id,
uint32_t queue_id)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);

uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

lock_srbm(kgd, mec, pipe, queue_id, 0);
lock_srbm(adev, mec, pipe, queue_id, 0);
}

static uint64_t get_queue_mask(struct amdgpu_device *adev,
Expand All @@ -80,9 +74,9 @@ static uint64_t get_queue_mask(struct amdgpu_device *adev,
return 1ull << bit;
}

static void release_queue(struct kgd_dev *kgd)
static void release_queue(struct amdgpu_device *adev)
{
unlock_srbm(kgd);
unlock_srbm(adev);
}

static void program_sh_mem_settings_v10_3(struct kgd_dev *kgd, uint32_t vmid,
Expand All @@ -93,13 +87,13 @@ static void program_sh_mem_settings_v10_3(struct kgd_dev *kgd, uint32_t vmid,
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);

lock_srbm(kgd, 0, 0, 0, vmid);
lock_srbm(adev, 0, 0, 0, vmid);

WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
/* APE1 no longer exists on GFX9 */

unlock_srbm(kgd);
unlock_srbm(adev);
}

/* ATC is defeatured on Sienna_Cichlid */
Expand Down Expand Up @@ -127,13 +121,13 @@ static int init_interrupts_v10_3(struct kgd_dev *kgd, uint32_t pipe_id)
mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

lock_srbm(kgd, mec, pipe, 0, 0);
lock_srbm(adev, mec, pipe, 0, 0);

WREG32_SOC15(GC, 0, mmCPC_INT_CNTL,
CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);

unlock_srbm(kgd);
unlock_srbm(adev);

return 0;
}
Expand Down Expand Up @@ -201,7 +195,7 @@ static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
m = get_mqd(mqd);

pr_debug("Load hqd of pipe %d queue %d\n", pipe_id, queue_id);
acquire_queue(kgd, pipe_id, queue_id);
acquire_queue(adev, pipe_id, queue_id);

/* HIQ is set during driver init period with vmid set to 0*/
if (m->cp_hqd_vmid == 0) {
Expand Down Expand Up @@ -281,7 +275,7 @@ static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data);

release_queue(kgd);
release_queue(adev);

return 0;
}
Expand All @@ -298,7 +292,7 @@ static int hiq_mqd_load_v10_3(struct kgd_dev *kgd, void *mqd,

m = get_mqd(mqd);

acquire_queue(kgd, pipe_id, queue_id);
acquire_queue(adev, pipe_id, queue_id);

mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
Expand Down Expand Up @@ -334,7 +328,7 @@ static int hiq_mqd_load_v10_3(struct kgd_dev *kgd, void *mqd,

out_unlock:
spin_unlock(&adev->gfx.kiq.ring_lock);
release_queue(kgd);
release_queue(adev);

return r;
}
Expand All @@ -357,13 +351,13 @@ static int hqd_dump_v10_3(struct kgd_dev *kgd,
if (*dump == NULL)
return -ENOMEM;

acquire_queue(kgd, pipe_id, queue_id);
acquire_queue(adev, pipe_id, queue_id);

for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
DUMP_REG(reg);

release_queue(kgd);
release_queue(adev);

WARN_ON_ONCE(i != HQD_N_REGS);
*n_regs = i;
Expand Down Expand Up @@ -481,7 +475,7 @@ static bool hqd_is_occupied_v10_3(struct kgd_dev *kgd, uint64_t queue_address,
bool retval = false;
uint32_t low, high;

acquire_queue(kgd, pipe_id, queue_id);
acquire_queue(adev, pipe_id, queue_id);
act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
if (act) {
low = lower_32_bits(queue_address >> 8);
Expand All @@ -491,7 +485,7 @@ static bool hqd_is_occupied_v10_3(struct kgd_dev *kgd, uint64_t queue_address,
high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI))
retval = true;
}
release_queue(kgd);
release_queue(adev);
return retval;
}

Expand Down Expand Up @@ -525,7 +519,7 @@ static int hqd_destroy_v10_3(struct kgd_dev *kgd, void *mqd,
uint32_t temp;
struct v10_compute_mqd *m = get_mqd(mqd);

acquire_queue(kgd, pipe_id, queue_id);
acquire_queue(adev, pipe_id, queue_id);

if (m->cp_hqd_vmid == 0)
WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0);
Expand Down Expand Up @@ -555,13 +549,13 @@ static int hqd_destroy_v10_3(struct kgd_dev *kgd, void *mqd,
if (time_after(jiffies, end_jiffies)) {
pr_err("cp queue pipe %d queue %d preemption failed\n",
pipe_id, queue_id);
release_queue(kgd);
release_queue(adev);
return -ETIME;
}
usleep_range(500, 1000);
}

release_queue(kgd);
release_queue(adev);
return 0;
}

Expand Down Expand Up @@ -666,7 +660,7 @@ static void program_trap_handler_settings_v10_3(struct kgd_dev *kgd,
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);

lock_srbm(kgd, 0, 0, 0, vmid);
lock_srbm(adev, 0, 0, 0, vmid);

/*
* Program TBA registers
Expand All @@ -685,7 +679,7 @@ static void program_trap_handler_settings_v10_3(struct kgd_dev *kgd,
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_HI),
upper_32_bits(tma_addr >> 8));

unlock_srbm(kgd);
unlock_srbm(adev);
}

#if 0
Expand Down

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