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net: microchip: sparx5: add support for offloading default prio
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Add support for offloading default prio {ETHERTYPE, 0, prio}.

Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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Daniel Machon authored and Paolo Abeni committed Nov 3, 2022
1 parent 8dcf69a commit c58ff3e
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Showing 3 changed files with 40 additions and 0 deletions.
12 changes: 12 additions & 0 deletions drivers/net/ethernet/microchip/sparx5/sparx5_dcb.c
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Original file line number Diff line number Diff line change
Expand Up @@ -49,6 +49,13 @@ static int sparx5_dcb_app_validate(struct net_device *dev,
int err = 0;

switch (app->selector) {
/* Default priority checks */
case IEEE_8021QAZ_APP_SEL_ETHERTYPE:
if (app->protocol != 0)
err = -EINVAL;
else if (app->priority >= SPX5_PRIOS)
err = -ERANGE;
break;
/* Dscp checks */
case IEEE_8021QAZ_APP_SEL_DSCP:
if (app->protocol >= SPARX5_PORT_QOS_DSCP_COUNT)
Expand Down Expand Up @@ -137,6 +144,11 @@ static int sparx5_dcb_app_update(struct net_device *dev)
dscp_map = &qos.dscp.map;
pcp_map = &qos.pcp.map;

/* Get default prio. */
qos.default_prio = dcb_ieee_getapp_default_prio_mask(dev);
if (qos.default_prio)
qos.default_prio = fls(qos.default_prio) - 1;

/* Get dscp ingress mapping */
for (i = 0; i < ARRAY_SIZE(dscp_map->map); i++) {
app_itr.selector = IEEE_8021QAZ_APP_SEL_DSCP;
Expand Down
23 changes: 23 additions & 0 deletions drivers/net/ethernet/microchip/sparx5/sparx5_port.c
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Expand Up @@ -1151,6 +1151,7 @@ int sparx5_port_qos_set(struct sparx5_port *port,
{
sparx5_port_qos_dscp_set(port, &qos->dscp);
sparx5_port_qos_pcp_set(port, &qos->pcp);
sparx5_port_qos_default_set(port, qos);

return 0;
}
Expand Down Expand Up @@ -1220,3 +1221,25 @@ int sparx5_port_qos_dscp_set(const struct sparx5_port *port,

return 0;
}

int sparx5_port_qos_default_set(const struct sparx5_port *port,
const struct sparx5_port_qos *qos)
{
struct sparx5 *sparx5 = port->sparx5;

/* Set default prio and dp level */
spx5_rmw(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_SET(qos->default_prio) |
ANA_CL_QOS_CFG_DEFAULT_DP_VAL_SET(0),
ANA_CL_QOS_CFG_DEFAULT_QOS_VAL |
ANA_CL_QOS_CFG_DEFAULT_DP_VAL,
sparx5, ANA_CL_QOS_CFG(port->portno));

/* Set default pcp and dei for untagged frames */
spx5_rmw(ANA_CL_VLAN_CTRL_PORT_PCP_SET(0) |
ANA_CL_VLAN_CTRL_PORT_DEI_SET(0),
ANA_CL_VLAN_CTRL_PORT_PCP |
ANA_CL_VLAN_CTRL_PORT_DEI,
sparx5, ANA_CL_VLAN_CTRL(port->portno));

return 0;
}
5 changes: 5 additions & 0 deletions drivers/net/ethernet/microchip/sparx5/sparx5_port.h
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Original file line number Diff line number Diff line change
Expand Up @@ -119,6 +119,7 @@ struct sparx5_port_qos_dscp {
struct sparx5_port_qos {
struct sparx5_port_qos_pcp pcp;
struct sparx5_port_qos_dscp dscp;
u8 default_prio;
};

int sparx5_port_qos_set(struct sparx5_port *port, struct sparx5_port_qos *qos);
Expand All @@ -128,4 +129,8 @@ int sparx5_port_qos_pcp_set(const struct sparx5_port *port,

int sparx5_port_qos_dscp_set(const struct sparx5_port *port,
struct sparx5_port_qos_dscp *qos);

int sparx5_port_qos_default_set(const struct sparx5_port *port,
const struct sparx5_port_qos *qos);

#endif /* __SPARX5_PORT_H__ */

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