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arm64: v8.3: Support for weaker release consistency
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ARMv8.3 adds new instructions to support Release Consistent
processor consistent (RCpc) model, which is weaker than the
RCsc model.

Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Suzuki K Poulose authored and Catalin Marinas committed Mar 20, 2017
1 parent cb567e7 commit c651aae
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Showing 5 changed files with 7 additions and 0 deletions.
2 changes: 2 additions & 0 deletions Documentation/arm64/cpu-feature-registers.txt
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Expand Up @@ -174,6 +174,8 @@ infrastructure:
x--------------------------------------------------x
| Name | bits | visible |
|--------------------------------------------------|
| LRCPC | [23-20] | y |
|--------------------------------------------------|
| FCMA | [19-16] | y |
|--------------------------------------------------|
| JSCVT | [15-12] | y |
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1 change: 1 addition & 0 deletions arch/arm64/include/asm/sysreg.h
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Expand Up @@ -157,6 +157,7 @@
#define ID_AA64ISAR0_AES_SHIFT 4

/* id_aa64isar1 */
#define ID_AA64ISAR1_LRCPC_SHIFT 20
#define ID_AA64ISAR1_FCMA_SHIFT 16
#define ID_AA64ISAR1_JSCVT_SHIFT 12

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1 change: 1 addition & 0 deletions arch/arm64/include/uapi/asm/hwcap.h
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Expand Up @@ -34,5 +34,6 @@
#define HWCAP_ASIMDRDM (1 << 12)
#define HWCAP_JSCVT (1 << 13)
#define HWCAP_FCMA (1 << 14)
#define HWCAP_LRCPC (1 << 15)

#endif /* _UAPI__ASM_HWCAP_H */
2 changes: 2 additions & 0 deletions arch/arm64/kernel/cpufeature.c
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Expand Up @@ -98,6 +98,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
};

static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
ARM64_FTR_END,
Expand Down Expand Up @@ -896,6 +897,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),
HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),
HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),
{},
};

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1 change: 1 addition & 0 deletions arch/arm64/kernel/cpuinfo.c
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Expand Up @@ -67,6 +67,7 @@ static const char *const hwcap_str[] = {
"asimdrdm",
"jscvt",
"fcma",
"lrcpc",
NULL
};

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