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| Original file line number | Diff line number | Diff line change |
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| Maxim MAX98504 class D mono speaker amplifier | ||
|
|
||
| This device supports I2C control interface and an IRQ output signal. It features | ||
| a PCM and PDM digital audio interface (DAI) and a differential analog input. | ||
|
|
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| Required properties: | ||
|
|
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| - compatible : "maxim,max98504" | ||
| - reg : should contain the I2C slave device address | ||
| - DVDD-supply, DIOVDD-supply, PVDD-supply: power supplies for the device, | ||
| as covered in ../regulator/regulator.txt | ||
| - interrupts : should specify the interrupt line the device is connected to, | ||
| as described in ../interrupt-controller/interrupts.txt | ||
|
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| Optional properties: | ||
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| - maxim,brownout-threshold - the PVDD brownout threshold, the value must be | ||
| from 0, 1...21 range, corresponding to 2.6V, 2.65V...3.65V voltage range | ||
| - maxim,brownout-attenuation - the brownout attenuation to the speaker gain | ||
| applied during the "attack hold" and "timed hold" phase, the value must be | ||
| from 0...6 (dB) range | ||
| - maxim,brownout-attack-hold-ms - the brownout attack hold phase time in ms, | ||
| 0...255 (VBATBROWN_ATTK_HOLD, register 0x0018) | ||
| - maxim,brownout-timed-hold-ms - the brownout timed hold phase time in ms, | ||
| 0...255 (VBATBROWN_TIME_HOLD, register 0x0019) | ||
| - maxim,brownout-release-rate-ms - the brownout release phase step time in ms, | ||
| 0...255 (VBATBROWN_RELEASE, register 0x001A) | ||
|
|
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| The default value when the above properties are not specified is 0, | ||
| the maxim,brownout-threshold property must be specified to actually enable | ||
| the PVDD brownout protection. | ||
|
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| Example: | ||
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| max98504@31 { | ||
| compatible = "maxim,max98504"; | ||
| reg = <0x31>; | ||
| interrupt-parent = <&gpio_bank_0>; | ||
| interrupts = <2 0>; | ||
|
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| DVDD-supply = <®ulator>; | ||
| DIOVDD-supply = <®ulator>; | ||
| PVDD-supply = <®ulator>; | ||
| }; |
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150
Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
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| Mediatek AFE PCM controller for mt2701 | ||
|
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||
| Required properties: | ||
| - compatible = "mediatek,mt2701-audio"; | ||
| - reg: register location and size | ||
| - interrupts: Should contain AFE interrupt | ||
| - clock-names: should have these clock names: | ||
| "infra_sys_audio_clk", | ||
| "top_audio_mux1_sel", | ||
| "top_audio_mux2_sel", | ||
| "top_audio_mux1_div", | ||
| "top_audio_mux2_div", | ||
| "top_audio_48k_timing", | ||
| "top_audio_44k_timing", | ||
| "top_audpll_mux_sel", | ||
| "top_apll_sel", | ||
| "top_aud1_pll_98M", | ||
| "top_aud2_pll_90M", | ||
| "top_hadds2_pll_98M", | ||
| "top_hadds2_pll_294M", | ||
| "top_audpll", | ||
| "top_audpll_d4", | ||
| "top_audpll_d8", | ||
| "top_audpll_d16", | ||
| "top_audpll_d24", | ||
| "top_audintbus_sel", | ||
| "clk_26m", | ||
| "top_syspll1_d4", | ||
| "top_aud_k1_src_sel", | ||
| "top_aud_k2_src_sel", | ||
| "top_aud_k3_src_sel", | ||
| "top_aud_k4_src_sel", | ||
| "top_aud_k5_src_sel", | ||
| "top_aud_k6_src_sel", | ||
| "top_aud_k1_src_div", | ||
| "top_aud_k2_src_div", | ||
| "top_aud_k3_src_div", | ||
| "top_aud_k4_src_div", | ||
| "top_aud_k5_src_div", | ||
| "top_aud_k6_src_div", | ||
| "top_aud_i2s1_mclk", | ||
| "top_aud_i2s2_mclk", | ||
| "top_aud_i2s3_mclk", | ||
| "top_aud_i2s4_mclk", | ||
| "top_aud_i2s5_mclk", | ||
| "top_aud_i2s6_mclk", | ||
| "top_asm_m_sel", | ||
| "top_asm_h_sel", | ||
| "top_univpll2_d4", | ||
| "top_univpll2_d2", | ||
| "top_syspll_d5"; | ||
|
|
||
| Example: | ||
|
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| afe: mt2701-afe-pcm@11220000 { | ||
| compatible = "mediatek,mt2701-audio"; | ||
| reg = <0 0x11220000 0 0x2000>, | ||
| <0 0x112A0000 0 0x20000>; | ||
| interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, | ||
| <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; | ||
| clocks = <&infracfg CLK_INFRA_AUDIO>, | ||
| <&topckgen CLK_TOP_AUD_MUX1_SEL>, | ||
| <&topckgen CLK_TOP_AUD_MUX2_SEL>, | ||
| <&topckgen CLK_TOP_AUD_MUX1_DIV>, | ||
| <&topckgen CLK_TOP_AUD_MUX2_DIV>, | ||
| <&topckgen CLK_TOP_AUD_48K_TIMING>, | ||
| <&topckgen CLK_TOP_AUD_44K_TIMING>, | ||
| <&topckgen CLK_TOP_AUDPLL_MUX_SEL>, | ||
| <&topckgen CLK_TOP_APLL_SEL>, | ||
| <&topckgen CLK_TOP_AUD1PLL_98M>, | ||
| <&topckgen CLK_TOP_AUD2PLL_90M>, | ||
| <&topckgen CLK_TOP_HADDS2PLL_98M>, | ||
| <&topckgen CLK_TOP_HADDS2PLL_294M>, | ||
| <&topckgen CLK_TOP_AUDPLL>, | ||
| <&topckgen CLK_TOP_AUDPLL_D4>, | ||
| <&topckgen CLK_TOP_AUDPLL_D8>, | ||
| <&topckgen CLK_TOP_AUDPLL_D16>, | ||
| <&topckgen CLK_TOP_AUDPLL_D24>, | ||
| <&topckgen CLK_TOP_AUDINTBUS_SEL>, | ||
| <&clk26m>, | ||
| <&topckgen CLK_TOP_SYSPLL1_D4>, | ||
| <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, | ||
| <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, | ||
| <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, | ||
| <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, | ||
| <&topckgen CLK_TOP_AUD_K5_SRC_SEL>, | ||
| <&topckgen CLK_TOP_AUD_K6_SRC_SEL>, | ||
| <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, | ||
| <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, | ||
| <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, | ||
| <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, | ||
| <&topckgen CLK_TOP_AUD_K5_SRC_DIV>, | ||
| <&topckgen CLK_TOP_AUD_K6_SRC_DIV>, | ||
| <&topckgen CLK_TOP_AUD_I2S1_MCLK>, | ||
| <&topckgen CLK_TOP_AUD_I2S2_MCLK>, | ||
| <&topckgen CLK_TOP_AUD_I2S3_MCLK>, | ||
| <&topckgen CLK_TOP_AUD_I2S4_MCLK>, | ||
| <&topckgen CLK_TOP_AUD_I2S5_MCLK>, | ||
| <&topckgen CLK_TOP_AUD_I2S6_MCLK>, | ||
| <&topckgen CLK_TOP_ASM_M_SEL>, | ||
| <&topckgen CLK_TOP_ASM_H_SEL>, | ||
| <&topckgen CLK_TOP_UNIVPLL2_D4>, | ||
| <&topckgen CLK_TOP_UNIVPLL2_D2>, | ||
| <&topckgen CLK_TOP_SYSPLL_D5>; | ||
|
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||
| clock-names = "infra_sys_audio_clk", | ||
| "top_audio_mux1_sel", | ||
| "top_audio_mux2_sel", | ||
| "top_audio_mux1_div", | ||
| "top_audio_mux2_div", | ||
| "top_audio_48k_timing", | ||
| "top_audio_44k_timing", | ||
| "top_audpll_mux_sel", | ||
| "top_apll_sel", | ||
| "top_aud1_pll_98M", | ||
| "top_aud2_pll_90M", | ||
| "top_hadds2_pll_98M", | ||
| "top_hadds2_pll_294M", | ||
| "top_audpll", | ||
| "top_audpll_d4", | ||
| "top_audpll_d8", | ||
| "top_audpll_d16", | ||
| "top_audpll_d24", | ||
| "top_audintbus_sel", | ||
| "clk_26m", | ||
| "top_syspll1_d4", | ||
| "top_aud_k1_src_sel", | ||
| "top_aud_k2_src_sel", | ||
| "top_aud_k3_src_sel", | ||
| "top_aud_k4_src_sel", | ||
| "top_aud_k5_src_sel", | ||
| "top_aud_k6_src_sel", | ||
| "top_aud_k1_src_div", | ||
| "top_aud_k2_src_div", | ||
| "top_aud_k3_src_div", | ||
| "top_aud_k4_src_div", | ||
| "top_aud_k5_src_div", | ||
| "top_aud_k6_src_div", | ||
| "top_aud_i2s1_mclk", | ||
| "top_aud_i2s2_mclk", | ||
| "top_aud_i2s3_mclk", | ||
| "top_aud_i2s4_mclk", | ||
| "top_aud_i2s5_mclk", | ||
| "top_aud_i2s6_mclk", | ||
| "top_asm_m_sel", | ||
| "top_asm_h_sel", | ||
| "top_univpll2_d4", | ||
| "top_univpll2_d2", | ||
| "top_syspll_d5"; | ||
| }; |
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43
Documentation/devicetree/bindings/sound/mt2701-cs42448.txt
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| MT2701 with CS42448 CODEC | ||
|
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| Required properties: | ||
| - compatible: "mediatek,mt2701-cs42448-machine" | ||
| - mediatek,platform: the phandle of MT2701 ASoC platform | ||
| - audio-routing: a list of the connections between audio | ||
| - mediatek,audio-codec: the phandles of cs42448 codec | ||
| - mediatek,audio-codec-bt-mrg the phandles of bt-sco dummy codec | ||
| - pinctrl-names: Should contain only one value - "default" | ||
| - pinctrl-0: Should specify pin control groups used for this controller. | ||
| - i2s1-in-sel-gpio1, i2s1-in-sel-gpio2: Should specify two gpio pins to | ||
| control I2S1-in mux. | ||
|
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| Example: | ||
|
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| sound:sound { | ||
| compatible = "mediatek,mt2701-cs42448-machine"; | ||
| mediatek,platform = <&afe>; | ||
| /* CS42448 Machine name */ | ||
| audio-routing = | ||
| "Line Out Jack", "AOUT1L", | ||
| "Line Out Jack", "AOUT1R", | ||
| "Line Out Jack", "AOUT2L", | ||
| "Line Out Jack", "AOUT2R", | ||
| "Line Out Jack", "AOUT3L", | ||
| "Line Out Jack", "AOUT3R", | ||
| "Line Out Jack", "AOUT4L", | ||
| "Line Out Jack", "AOUT4R", | ||
| "AIN1L", "AMIC", | ||
| "AIN1R", "AMIC", | ||
| "AIN2L", "Tuner In", | ||
| "AIN2R", "Tuner In", | ||
| "AIN3L", "Satellite Tuner In", | ||
| "AIN3R", "Satellite Tuner In", | ||
| "AIN3L", "AUX In", | ||
| "AIN3R", "AUX In"; | ||
| mediatek,audio-codec = <&cs42448>; | ||
| mediatek,audio-codec-bt-mrg = <&bt_sco_codec>; | ||
| pinctrl-names = "default"; | ||
| pinctrl-0 = <&aud_pins_default>; | ||
| i2s1-in-sel-gpio1 = <&pio 53 0>; | ||
| i2s1-in-sel-gpio2 = <&pio 54 0>; | ||
| }; |
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