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amd-xgbe: Optimize DMA channel interrupt enablement
Currently whenever the driver needs to enable or disable interrupts for a DMA channel it reads the interrupt enable register (IER), updates the value and then writes the new value back to the IER. Since the hardware does not change the IER, software can track this value and elimiate the need to read it each time. Add the IER value to the channel related data structure and use that as the base for enabling and disabling interrupts, thus removing the need for the MMIO read. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Lendacky, Thomas
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David S. Miller
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Aug 18, 2017
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