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Merge branch '/jinhuang/rocm-rel-1.9-pp' into rocm-rel-1.9
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It is to enable powerplay for Vega20.

Change-Id: I8a111e7a9706ff0718a18adbe210a5dd3d1a6c4c
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
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Eric Huang authored and Eric Huang committed Sep 13, 2018
2 parents 1dc4684 + cb460ac commit cbd770d
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Showing 64 changed files with 70,067 additions and 190 deletions.
5 changes: 3 additions & 2 deletions drivers/gpu/drm/amd/amdgpu/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -62,7 +62,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce

amdgpu-y += \
vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
vega20_reg_init.o
vega20_reg_init.o nbio_v7_4.o

# add DF block
amdgpu-y += \
Expand All @@ -88,7 +88,8 @@ amdgpu-y += \
amdgpu-y += \
amdgpu_psp.o \
psp_v3_1.o \
psp_v10_0.o
psp_v10_0.o \
psp_v11_0.o

# add SMC block
amdgpu-y += \
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12 changes: 6 additions & 6 deletions drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
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Expand Up @@ -565,12 +565,12 @@ static const struct pci_device_id pciidlist[] = {
{0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
{0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
/* Vega 20 */
{0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20|AMD_EXP_HW_SUPPORT},
{0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20|AMD_EXP_HW_SUPPORT},
{0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20|AMD_EXP_HW_SUPPORT},
{0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20|AMD_EXP_HW_SUPPORT},
{0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20|AMD_EXP_HW_SUPPORT},
{0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20|AMD_EXP_HW_SUPPORT},
{0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
{0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
{0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
{0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
{0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
{0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
/* Raven */
{0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},

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20 changes: 17 additions & 3 deletions drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
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Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,7 @@
#include "soc15_common.h"
#include "psp_v3_1.h"
#include "psp_v10_0.h"
#include "psp_v11_0.h"

static void psp_set_funcs(struct amdgpu_device *adev);

Expand All @@ -52,12 +53,14 @@ static int psp_sw_init(void *handle)
switch (adev->asic_type) {
case CHIP_VEGA10:
case CHIP_VEGA12:
case CHIP_VEGA20:
psp_v3_1_set_psp_funcs(psp);
break;
case CHIP_RAVEN:
psp_v10_0_set_psp_funcs(psp);
break;
case CHIP_VEGA20:
psp_v11_0_set_psp_funcs(psp);
break;
default:
return -EINVAL;
}
Expand Down Expand Up @@ -155,7 +158,7 @@ static int psp_tmr_init(struct psp_context *psp)
* Note: this memory need be reserved till the driver
* uninitializes.
*/
ret = amdgpu_bo_create_kernel(psp->adev, 0x300000, 0x100000,
ret = amdgpu_bo_create_kernel(psp->adev, PSP_TMR_SIZE, 0x100000,
AMDGPU_GEM_DOMAIN_VRAM,
&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);

Expand All @@ -171,7 +174,9 @@ static int psp_tmr_load(struct psp_context *psp)
if (!cmd)
return -ENOMEM;

psp_prep_tmr_cmd_buf(cmd, psp->tmr_mc_addr, 0x300000);
psp_prep_tmr_cmd_buf(cmd, psp->tmr_mc_addr, PSP_TMR_SIZE);
DRM_INFO("reserve 0x%x from 0x%llx for PSP TMR SIZE\n",
PSP_TMR_SIZE, psp->tmr_mc_addr);

ret = psp_cmd_submit_buf(psp, NULL, cmd,
psp->fence_buf_mc_addr, 1);
Expand Down Expand Up @@ -589,3 +594,12 @@ const struct amdgpu_ip_block_version psp_v10_0_ip_block =
.rev = 0,
.funcs = &psp_ip_funcs,
};

const struct amdgpu_ip_block_version psp_v11_0_ip_block =
{
.type = AMD_IP_BLOCK_TYPE_PSP,
.major = 11,
.minor = 0,
.rev = 0,
.funcs = &psp_ip_funcs,
};
2 changes: 2 additions & 0 deletions drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
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Original file line number Diff line number Diff line change
Expand Up @@ -32,6 +32,7 @@
#define PSP_CMD_BUFFER_SIZE 0x1000
#define PSP_ASD_SHARED_MEM_SIZE 0x4000
#define PSP_1_MEG 0x100000
#define PSP_TMR_SIZE 0x400000

struct psp_context;

Expand Down Expand Up @@ -159,5 +160,6 @@ extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;

int psp_gpu_reset(struct amdgpu_device *adev);
extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;

#endif
3 changes: 1 addition & 2 deletions drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
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Expand Up @@ -303,12 +303,11 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
case CHIP_VEGA10:
case CHIP_RAVEN:
case CHIP_VEGA12:
case CHIP_VEGA20:
if (!load_type)
return AMDGPU_FW_LOAD_DIRECT;
else
return AMDGPU_FW_LOAD_PSP;
case CHIP_VEGA20:
return AMDGPU_FW_LOAD_DIRECT;
default:
DRM_ERROR("Unknow firmware load type\n");
}
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1 change: 1 addition & 0 deletions drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
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Original file line number Diff line number Diff line change
Expand Up @@ -193,6 +193,7 @@ enum AMDGPU_UCODE_ID {
AMDGPU_UCODE_ID_STORAGE,
AMDGPU_UCODE_ID_SMC,
AMDGPU_UCODE_ID_UVD,
AMDGPU_UCODE_ID_UVD1,
AMDGPU_UCODE_ID_VCE,
AMDGPU_UCODE_ID_MAXIMUM,
};
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2 changes: 1 addition & 1 deletion drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
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Original file line number Diff line number Diff line change
Expand Up @@ -80,7 +80,7 @@ MODULE_FIRMWARE("amdgpu/raven_rlc.bin");

static const struct soc15_reg_golden golden_settings_gc_9_0[] =
{
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
Expand Down
18 changes: 1 addition & 17 deletions drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
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Original file line number Diff line number Diff line change
Expand Up @@ -34,19 +34,10 @@
#define smnCPM_CONTROL 0x11180460
#define smnPCIE_CNTL2 0x11180070

/* vega20 */
#define mmRCC_DEV0_EPF0_STRAP0_VG20 0x0011
#define mmRCC_DEV0_EPF0_STRAP0_VG20_BASE_IDX 2

static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
{
u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);

if (adev->asic_type == CHIP_VEGA20)
tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0_VG20);
else
tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);

tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;

Expand Down Expand Up @@ -84,14 +75,10 @@ static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instan
SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);

u32 doorbell_range = RREG32(reg);
u32 range = 2;

if (adev->asic_type == CHIP_VEGA20)
range = 8;

if (use_doorbell) {
doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, range);
doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
} else
doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);

Expand Down Expand Up @@ -146,9 +133,6 @@ static void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *ade
{
uint32_t def, data;

if (adev->asic_type == CHIP_VEGA20)
return;

/* NBIF_MGCG_CTRL_LCLK */
def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);

Expand Down
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