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clk: qoriq: add more PLL divider clocks support
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More PLL divider clocks are needed by clock consumer IP. So enlarge
the PLL divider array to accommodate more divider clocks.

Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Yuantian Tang authored and Stephen Boyd committed Apr 25, 2019
1 parent f34b2c2 commit cc61ab9
Showing 1 changed file with 3 additions and 2 deletions.
5 changes: 3 additions & 2 deletions drivers/clk/clk-qoriq.c
Original file line number Diff line number Diff line change
Expand Up @@ -34,14 +34,15 @@
#define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
#define CGB_PLL1 4
#define CGB_PLL2 5
#define MAX_PLL_DIV 16

struct clockgen_pll_div {
struct clk *clk;
char name[32];
};

struct clockgen_pll {
struct clockgen_pll_div div[8];
struct clockgen_pll_div div[MAX_PLL_DIV];
};

#define CLKSEL_VALID 1
Expand Down Expand Up @@ -1128,7 +1129,7 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
int ret;

/*
* For platform PLL, there are 8 divider clocks.
* For platform PLL, there are MAX_PLL_DIV divider clocks.
* For core PLL, there are 4 divider clocks at most.
*/
if (idx != PLATFORM_PLL && i >= 4)
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