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drm/sun4i: hdmi: Allow using second PLL as TMDS clk parent
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On SoCs with two display pipelines, it is possible that the two
pipelines are active at the same time, with potentially incompatible
dot clocks.

Let the HDMI encoder's TMDS clock go through all of its parents when
calculating possible clock rates. This allows usage of the second video
PLL as its parent.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171010032008.682-6-wens@csie.org
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Chen-Yu Tsai authored and Maxime Ripard committed Oct 11, 2017
1 parent 4b1c924 commit cc67ae9
Showing 1 changed file with 29 additions and 24 deletions.
53 changes: 29 additions & 24 deletions drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
Original file line number Diff line number Diff line change
Expand Up @@ -67,44 +67,49 @@ static unsigned long sun4i_tmds_calc_divider(unsigned long rate,
static int sun4i_tmds_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_hw *parent;
struct clk_hw *parent = NULL;
unsigned long best_parent = 0;
unsigned long rate = req->rate;
int best_div = 1, best_half = 1;
int i, j;
int i, j, p;

/*
* We only consider PLL3, since the TCON is very likely to be
* clocked from it, and to have the same rate than our HDMI
* clock, so we should not need to do anything.
*/

parent = clk_hw_get_parent_by_index(hw, 0);
if (!parent)
return -EINVAL;

for (i = 1; i < 3; i++) {
for (j = 1; j < 16; j++) {
unsigned long ideal = rate * i * j;
unsigned long rounded;

rounded = clk_hw_round_rate(parent, ideal);

if (rounded == ideal) {
best_parent = rounded;
best_half = i;
best_div = j;
goto out;
}

if (abs(rate - rounded / i) <
abs(rate - best_parent / best_div)) {
best_parent = rounded;
best_div = i;
for (p = 0; p < clk_hw_get_num_parents(hw); p++) {
parent = clk_hw_get_parent_by_index(hw, p);
if (!parent)
continue;

for (i = 1; i < 3; i++) {
for (j = 1; j < 16; j++) {
unsigned long ideal = rate * i * j;
unsigned long rounded;

rounded = clk_hw_round_rate(parent, ideal);

if (rounded == ideal) {
best_parent = rounded;
best_half = i;
best_div = j;
goto out;
}

if (abs(rate - rounded / i) <
abs(rate - best_parent / best_div)) {
best_parent = rounded;
best_div = i;
}
}
}
}

if (!parent)
return -EINVAL;

out:
req->rate = best_parent / best_half / best_div;
req->best_parent_rate = best_parent;
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