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Fix preemption and SMP problems in the FP emulator code.
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle committed Oct 29, 2005
1 parent 63b2d2f commit cd21dfc
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Showing 5 changed files with 122 additions and 119 deletions.
19 changes: 17 additions & 2 deletions arch/mips/kernel/traps.c
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Original file line number Diff line number Diff line change
Expand Up @@ -551,6 +551,14 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)

preempt_disable();

#ifdef CONFIG_PREEMPT
if (!is_fpu_owner()) {
/* We might lose fpu before disabling preempt... */
own_fpu();
BUG_ON(!used_math());
restore_fp(current);
}
#endif
/*
* Unimplemented operation exception. If we've got the full
* software emulator on-board, let's use it...
Expand All @@ -562,11 +570,18 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
* a bit extreme for what should be an infrequent event.
*/
save_fp(current);
/* Ensure 'resume' not overwrite saved fp context again. */
lose_fpu();

preempt_enable();

/* Run the emulator */
sig = fpu_emulator_cop1Handler (0, regs,
&current->thread.fpu.soft);

preempt_disable();

own_fpu(); /* Using the FPU again. */
/*
* We can't allow the emulated instruction to leave any of
* the cause bit set in $fcr31.
Expand Down Expand Up @@ -712,15 +727,15 @@ asmlinkage void do_cpu(struct pt_regs *regs)
set_used_math();
}

preempt_enable();

if (!cpu_has_fpu) {
int sig = fpu_emulator_cop1Handler(0, regs,
&current->thread.fpu.soft);
if (sig)
force_sig(sig, current);
}

preempt_enable();

return;

case 2:
Expand Down
41 changes: 27 additions & 14 deletions arch/mips/math-emu/cp1emu.c
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Original file line number Diff line number Diff line change
Expand Up @@ -79,7 +79,17 @@ struct mips_fpu_emulator_private fpuemuprivate;

/* Convert Mips rounding mode (0..3) to IEEE library modes. */
static const unsigned char ieee_rm[4] = {
IEEE754_RN, IEEE754_RZ, IEEE754_RU, IEEE754_RD
[FPU_CSR_RN] = IEEE754_RN,
[FPU_CSR_RZ] = IEEE754_RZ,
[FPU_CSR_RU] = IEEE754_RU,
[FPU_CSR_RD] = IEEE754_RD,
};
/* Convert IEEE library modes to Mips rounding mode (0..3). */
static const unsigned char mips_rm[4] = {
[IEEE754_RN] = FPU_CSR_RN,
[IEEE754_RZ] = FPU_CSR_RZ,
[IEEE754_RD] = FPU_CSR_RD,
[IEEE754_RU] = FPU_CSR_RU,
};

#if __mips >= 4
Expand Down Expand Up @@ -368,6 +378,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
}
if (MIPSInst_RD(ir) == FPCREG_CSR) {
value = ctx->fcr31;
value = (value & ~0x3) | mips_rm[value & 0x3];
#ifdef CSRTRACE
printk("%p gpr[%d]<-csr=%08x\n",
(void *) (xcp->cp0_epc),
Expand Down Expand Up @@ -400,11 +411,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
(void *) (xcp->cp0_epc),
MIPSInst_RT(ir), value);
#endif
ctx->fcr31 = value;
/* copy new rounding mode and
flush bit to ieee library state! */
ieee754_csr.nod = (ctx->fcr31 & 0x1000000) != 0;
ieee754_csr.rm = ieee_rm[value & 0x3];
value &= (FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03);
ctx->fcr31 &= ~(FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03);
/* convert to ieee library modes */
ctx->fcr31 |= (value & ~0x3) | ieee_rm[value & 0x3];
}
if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
return SIGFPE;
Expand Down Expand Up @@ -570,7 +580,7 @@ static const unsigned char cmptab[8] = {
static ieee754##p fpemu_##p##_##name (ieee754##p r, ieee754##p s, \
ieee754##p t) \
{ \
struct ieee754_csr ieee754_csr_save; \
struct _ieee754_csr ieee754_csr_save; \
s = f1 (s, t); \
ieee754_csr_save = ieee754_csr; \
s = f2 (s, r); \
Expand Down Expand Up @@ -699,8 +709,6 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;

ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
if (ieee754_csr.nod)
ctx->fcr31 |= 0x1000000;
if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
/*printk ("SIGFPE: fpu csr = %08x\n",
ctx->fcr31); */
Expand Down Expand Up @@ -1297,12 +1305,17 @@ int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp,
if (insn == 0)
xcp->cp0_epc += 4; /* skip nops */
else {
/* Update ieee754_csr. Only relevant if we have a
h/w FPU */
ieee754_csr.nod = (ctx->fcr31 & 0x1000000) != 0;
ieee754_csr.rm = ieee_rm[ctx->fcr31 & 0x3];
ieee754_csr.cx = (ctx->fcr31 >> 12) & 0x1f;
/*
* The 'ieee754_csr' is an alias of
* ctx->fcr31. No need to copy ctx->fcr31 to
* ieee754_csr. But ieee754_csr.rm is ieee
* library modes. (not mips rounding mode)
*/
/* convert to ieee library modes */
ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
sig = cop1Emulate(xcp, ctx);
/* revert to mips rounding mode */
ieee754_csr.rm = mips_rm[ieee754_csr.rm];
}

if (cpu_has_fpu)
Expand Down
2 changes: 1 addition & 1 deletion arch/mips/math-emu/dp_sqrt.c
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Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,7 @@ static const unsigned table[] = {

ieee754dp ieee754dp_sqrt(ieee754dp x)
{
struct ieee754_csr oldcsr;
struct _ieee754_csr oldcsr;
ieee754dp y, z, t;
unsigned scalx, yh;
COMPXDP;
Expand Down
4 changes: 0 additions & 4 deletions arch/mips/math-emu/ieee754.c
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Original file line number Diff line number Diff line change
Expand Up @@ -50,10 +50,6 @@ const char *const ieee754_cname[] = {
"SNaN",
};

/* the control status register
*/
struct ieee754_csr ieee754_csr;

/* special constants
*/

Expand Down
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