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ARM: dts: exynos: Remove "cooling-{min|max}-level" for CPU nodes
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The "cooling-min-level" and "cooling-max-level" properties are not
parsed by any part of the kernel currently and the max cooling state of
a CPU cooling device is found by referring to the cpufreq table instead.

Remove the unused properties from the CPU nodes.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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Viresh Kumar authored and Krzysztof Kozlowski committed Feb 13, 2018
1 parent bd010d6 commit cd6f554
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Showing 5 changed files with 0 additions and 38 deletions.
2 changes: 0 additions & 2 deletions arch/arm/boot/dts/exynos4210.dtsi
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Expand Up @@ -48,8 +48,6 @@
400000 975000
200000 950000
>;
cooling-min-level = <4>;
cooling-max-level = <2>;
#cooling-cells = <2>; /* min followed by max */
};

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2 changes: 0 additions & 2 deletions arch/arm/boot/dts/exynos4412.dtsi
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Expand Up @@ -42,8 +42,6 @@
clocks = <&clock CLK_ARM_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
cooling-min-level = <13>;
cooling-max-level = <7>;
#cooling-cells = <2>; /* min followed by max */
};

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2 changes: 0 additions & 2 deletions arch/arm/boot/dts/exynos5250.dtsi
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Expand Up @@ -77,8 +77,6 @@
300000 937500
200000 925000
>;
cooling-min-level = <15>;
cooling-max-level = <9>;
#cooling-cells = <2>; /* min followed by max */
};
cpu@1 {
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16 changes: 0 additions & 16 deletions arch/arm/boot/dts/exynos5420-cpus.dtsi
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Expand Up @@ -30,8 +30,6 @@
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <1024>;
};
Expand All @@ -43,8 +41,6 @@
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <1024>;
};
Expand All @@ -56,8 +52,6 @@
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <1024>;
};
Expand All @@ -69,8 +63,6 @@
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <1024>;
};
Expand All @@ -83,8 +75,6 @@
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <7>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <539>;
};
Expand All @@ -96,8 +86,6 @@
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <7>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <539>;
};
Expand All @@ -109,8 +97,6 @@
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <7>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <539>;
};
Expand All @@ -122,8 +108,6 @@
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <7>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <539>;
};
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16 changes: 0 additions & 16 deletions arch/arm/boot/dts/exynos5422-cpus.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -29,8 +29,6 @@
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <539>;
};
Expand All @@ -42,8 +40,6 @@
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <539>;
};
Expand All @@ -55,8 +51,6 @@
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <539>;
};
Expand All @@ -68,8 +62,6 @@
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <539>;
};
Expand All @@ -82,8 +74,6 @@
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <15>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <1024>;
};
Expand All @@ -95,8 +85,6 @@
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <15>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <1024>;
};
Expand All @@ -108,8 +96,6 @@
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <15>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <1024>;
};
Expand All @@ -121,8 +107,6 @@
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <15>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <1024>;
};
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