UBUNTU: SAUCE: xhci: workaround for S3 issue on AMD SNPS 3.0 xHC

BugLink: https://bugs.launchpad.net/bugs/1893914

On some platform of AMD, S3 fails with HCE and SRE errors.To fix this,
sparse controller enable bit has to be disabled.

Signed-off-by: Nehal Bakulchandra Shah <Nehal-Bakulchandra.shah@amd.com>
(backported from https://lkml.org/lkml/2020/8/31/86)
Signed-off-by: Aaron Ma <aaron.ma@canonical.com>
Signed-off-by: Timo Aaltonen <timo.aaltonen@canonical.com>

drivers/usb/host/xhci-pci.c

@@ -147,6 +147,9 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
 	    (pdev->device == 0x15e0 || pdev->device == 0x15e1))
 		xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
 
+	if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5)
+		xhci->quirks |= XHCI_DISABLE_SPARSE;
+
 	if (pdev->vendor == PCI_VENDOR_ID_AMD)
 		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 
@@ -346,6 +349,15 @@ static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 	/* USB 2.0 roothub is stored in the PCI device now. */
 	hcd = dev_get_drvdata(&dev->dev);
 	xhci = hcd_to_xhci(hcd);
+
+	if (xhci->quirks & XHCI_DISABLE_SPARSE) {
+		u32 reg;
+
+		reg = readl(hcd->regs + 0xC12C);
+		reg &=  ~BIT(17);
+		writel(reg, hcd->regs + 0xC12C);
+	}
+
 	xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
 				pci_name(dev), hcd);
 	if (!xhci->shared_hcd) {

drivers/usb/host/xhci.h

@@ -1873,6 +1873,7 @@ struct xhci_hcd {
 #define XHCI_DEFAULT_PM_RUNTIME_ALLOW	BIT_ULL(33)
 #define XHCI_RESET_PLL_ON_DISCONNECT	BIT_ULL(34)
 #define XHCI_SNPS_BROKEN_SUSPEND    BIT_ULL(35)
+#define XHCI_DISABLE_SPARSE	BIT_ULL(37)
 
 	unsigned int		num_active_eps;
 	unsigned int		limit_active_eps;