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perf stat: Fix the ratio comments of miss-events
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'perf stat' displays miss ratio of L1-dcache, L1-icache, dTLB cache,
iTLB cache and LL-cache. Take L1-dcache for example, miss ratio is
caculated as "L1-dcache-load-misses/L1-dcache-loads". So "of all
L1-dcache hits" is unsuitable to describe it, and "of all L1-dcache
accesses" seems better.

The comments of L1-icache, dTLB cache, iTLB cache and LL-cache are
fixed in the same way.

Signed-off-by: Qi Liu <liuqi115@huawei.com>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Cc: linuxarm@huawei.com
Link: http://lore.kernel.org/lkml/1600253331-10535-1-git-send-email-liuqi115@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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Qi Liu authored and Arnaldo Carvalho de Melo committed Sep 16, 2020
1 parent d26383d commit ce9c13f
Showing 1 changed file with 10 additions and 10 deletions.
20 changes: 10 additions & 10 deletions tools/perf/util/stat-shadow.c
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Original file line number Diff line number Diff line change
Expand Up @@ -517,7 +517,7 @@ static void print_l1_dcache_misses(struct perf_stat_config *config,

color = get_ratio_color(GRC_CACHE_MISSES, ratio);

out->print_metric(config, out->ctx, color, "%7.2f%%", "of all L1-dcache hits", ratio);
out->print_metric(config, out->ctx, color, "%7.2f%%", "of all L1-dcache accesses", ratio);
}

static void print_l1_icache_misses(struct perf_stat_config *config,
Expand All @@ -538,7 +538,7 @@ static void print_l1_icache_misses(struct perf_stat_config *config,
ratio = avg / total * 100.0;

color = get_ratio_color(GRC_CACHE_MISSES, ratio);
out->print_metric(config, out->ctx, color, "%7.2f%%", "of all L1-icache hits", ratio);
out->print_metric(config, out->ctx, color, "%7.2f%%", "of all L1-icache accesses", ratio);
}

static void print_dtlb_cache_misses(struct perf_stat_config *config,
Expand All @@ -558,7 +558,7 @@ static void print_dtlb_cache_misses(struct perf_stat_config *config,
ratio = avg / total * 100.0;

color = get_ratio_color(GRC_CACHE_MISSES, ratio);
out->print_metric(config, out->ctx, color, "%7.2f%%", "of all dTLB cache hits", ratio);
out->print_metric(config, out->ctx, color, "%7.2f%%", "of all dTLB cache accesses", ratio);
}

static void print_itlb_cache_misses(struct perf_stat_config *config,
Expand All @@ -578,7 +578,7 @@ static void print_itlb_cache_misses(struct perf_stat_config *config,
ratio = avg / total * 100.0;

color = get_ratio_color(GRC_CACHE_MISSES, ratio);
out->print_metric(config, out->ctx, color, "%7.2f%%", "of all iTLB cache hits", ratio);
out->print_metric(config, out->ctx, color, "%7.2f%%", "of all iTLB cache accesses", ratio);
}

static void print_ll_cache_misses(struct perf_stat_config *config,
Expand All @@ -598,7 +598,7 @@ static void print_ll_cache_misses(struct perf_stat_config *config,
ratio = avg / total * 100.0;

color = get_ratio_color(GRC_CACHE_MISSES, ratio);
out->print_metric(config, out->ctx, color, "%7.2f%%", "of all LL-cache hits", ratio);
out->print_metric(config, out->ctx, color, "%7.2f%%", "of all LL-cache accesses", ratio);
}

/*
Expand Down Expand Up @@ -920,7 +920,7 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config,
if (runtime_stat_n(st, STAT_L1_DCACHE, ctx, cpu) != 0)
print_l1_dcache_misses(config, cpu, evsel, avg, out, st);
else
print_metric(config, ctxp, NULL, NULL, "of all L1-dcache hits", 0);
print_metric(config, ctxp, NULL, NULL, "of all L1-dcache accesses", 0);
} else if (
evsel->core.attr.type == PERF_TYPE_HW_CACHE &&
evsel->core.attr.config == ( PERF_COUNT_HW_CACHE_L1I |
Expand All @@ -930,7 +930,7 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config,
if (runtime_stat_n(st, STAT_L1_ICACHE, ctx, cpu) != 0)
print_l1_icache_misses(config, cpu, evsel, avg, out, st);
else
print_metric(config, ctxp, NULL, NULL, "of all L1-icache hits", 0);
print_metric(config, ctxp, NULL, NULL, "of all L1-icache accesses", 0);
} else if (
evsel->core.attr.type == PERF_TYPE_HW_CACHE &&
evsel->core.attr.config == ( PERF_COUNT_HW_CACHE_DTLB |
Expand All @@ -940,7 +940,7 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config,
if (runtime_stat_n(st, STAT_DTLB_CACHE, ctx, cpu) != 0)
print_dtlb_cache_misses(config, cpu, evsel, avg, out, st);
else
print_metric(config, ctxp, NULL, NULL, "of all dTLB cache hits", 0);
print_metric(config, ctxp, NULL, NULL, "of all dTLB cache accesses", 0);
} else if (
evsel->core.attr.type == PERF_TYPE_HW_CACHE &&
evsel->core.attr.config == ( PERF_COUNT_HW_CACHE_ITLB |
Expand All @@ -950,7 +950,7 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config,
if (runtime_stat_n(st, STAT_ITLB_CACHE, ctx, cpu) != 0)
print_itlb_cache_misses(config, cpu, evsel, avg, out, st);
else
print_metric(config, ctxp, NULL, NULL, "of all iTLB cache hits", 0);
print_metric(config, ctxp, NULL, NULL, "of all iTLB cache accesses", 0);
} else if (
evsel->core.attr.type == PERF_TYPE_HW_CACHE &&
evsel->core.attr.config == ( PERF_COUNT_HW_CACHE_LL |
Expand All @@ -960,7 +960,7 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config,
if (runtime_stat_n(st, STAT_LL_CACHE, ctx, cpu) != 0)
print_ll_cache_misses(config, cpu, evsel, avg, out, st);
else
print_metric(config, ctxp, NULL, NULL, "of all LL-cache hits", 0);
print_metric(config, ctxp, NULL, NULL, "of all LL-cache accesses", 0);
} else if (evsel__match(evsel, HARDWARE, HW_CACHE_MISSES)) {
total = runtime_stat_avg(st, STAT_CACHEREFS, ctx, cpu);

Expand Down

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