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dt-bindings: net: Add Motorcomm yt8xxx ethernet phy
Add a YAML binding document for the Motorcomm yt8xxx Ethernet phy. Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/net/motorcomm,yt8xxx.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: MotorComm yt8xxx Ethernet PHY | ||
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maintainers: | ||
- Frank Sae <frank.sae@motor-comm.com> | ||
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allOf: | ||
- $ref: ethernet-phy.yaml# | ||
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properties: | ||
compatible: | ||
enum: | ||
- ethernet-phy-id4f51.e91a | ||
- ethernet-phy-id4f51.e91b | ||
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rx-internal-delay-ps: | ||
description: | | ||
RGMII RX Clock Delay used only when PHY operates in RGMII mode with | ||
internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds. | ||
enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650, | ||
1800, 1900, 1950, 2050, 2100, 2200, 2250, 2350, 2500, 2650, 2800, | ||
2950, 3100, 3250, 3400, 3550, 3700, 3850, 4000, 4150 ] | ||
default: 1950 | ||
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tx-internal-delay-ps: | ||
description: | | ||
RGMII TX Clock Delay used only when PHY operates in RGMII mode with | ||
internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds. | ||
enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650, 1800, | ||
1950, 2100, 2250 ] | ||
default: 1950 | ||
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motorcomm,clk-out-frequency-hz: | ||
description: clock output on clock output pin. | ||
enum: [0, 25000000, 125000000] | ||
default: 0 | ||
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motorcomm,keep-pll-enabled: | ||
description: | | ||
If set, keep the PLL enabled even if there is no link. Useful if you | ||
want to use the clock output without an ethernet link. | ||
type: boolean | ||
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motorcomm,auto-sleep-disabled: | ||
description: | | ||
If set, PHY will not enter sleep mode and close AFE after unplug cable | ||
for a timer. | ||
type: boolean | ||
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motorcomm,tx-clk-adj-enabled: | ||
description: | | ||
This configuration is mainly to adapt to VF2 with JH7110 SoC. | ||
Useful if you want to use tx-clk-xxxx-inverted to adj the delay of tx clk. | ||
type: boolean | ||
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motorcomm,tx-clk-10-inverted: | ||
description: | | ||
Use original or inverted RGMII Transmit PHY Clock to drive the RGMII | ||
Transmit PHY Clock delay train configuration when speed is 10Mbps. | ||
type: boolean | ||
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motorcomm,tx-clk-100-inverted: | ||
description: | | ||
Use original or inverted RGMII Transmit PHY Clock to drive the RGMII | ||
Transmit PHY Clock delay train configuration when speed is 100Mbps. | ||
type: boolean | ||
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motorcomm,tx-clk-1000-inverted: | ||
description: | | ||
Use original or inverted RGMII Transmit PHY Clock to drive the RGMII | ||
Transmit PHY Clock delay train configuration when speed is 1000Mbps. | ||
type: boolean | ||
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unevaluatedProperties: false | ||
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examples: | ||
- | | ||
mdio { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
phy-mode = "rgmii-id"; | ||
ethernet-phy@4 { | ||
/* Only needed to make DT lint tools work. Do not copy/paste | ||
* into real DTS files. | ||
*/ | ||
compatible = "ethernet-phy-id4f51.e91a"; | ||
reg = <4>; | ||
rx-internal-delay-ps = <2100>; | ||
tx-internal-delay-ps = <150>; | ||
motorcomm,clk-out-frequency-hz = <0>; | ||
motorcomm,keep-pll-enabled; | ||
motorcomm,auto-sleep-disabled; | ||
}; | ||
}; | ||
- | | ||
mdio { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
phy-mode = "rgmii"; | ||
ethernet-phy@5 { | ||
/* Only needed to make DT lint tools work. Do not copy/paste | ||
* into real DTS files. | ||
*/ | ||
compatible = "ethernet-phy-id4f51.e91a"; | ||
reg = <5>; | ||
motorcomm,clk-out-frequency-hz = <125000000>; | ||
motorcomm,keep-pll-enabled; | ||
motorcomm,auto-sleep-disabled; | ||
}; | ||
}; |
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