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octeontx2-af: cn10k: mcs: Manage the MCS block hardware resources
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To establish a macsec connection association netdev driver
needs hardware resources like SecY, TCAM flows, SCs and SAs.
This patch manages allocating, freeing and configuring those
resources. AF consumers can request resources and configure them
via these mailbox messages. AF can allocate until it runs out of
hardware resources.

Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Geetha sowjanya authored and David S. Miller committed Oct 3, 2022
1 parent 080bbd1 commit cfc1418
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211 changes: 211 additions & 0 deletions drivers/net/ethernet/marvell/octeontx2/af/mbox.h
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Original file line number Diff line number Diff line change
Expand Up @@ -295,10 +295,38 @@ M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \
M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \
nix_bandprof_get_hwinfo_rsp) \
/* MCS mbox IDs (range 0xA000 - 0xBFFF) */ \
M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \
mcs_alloc_rsrc_rsp) \
M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \
M(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, mcs_flowid_entry_write_req, \
msg_rsp) \
M(MCS_SECY_PLCY_WRITE, 0xa003, mcs_secy_plcy_write, mcs_secy_plcy_write_req, \
msg_rsp) \
M(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, \
msg_rsp) \
M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, \
msg_rsp) \
M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, \
msg_rsp) \
M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, \
msg_rsp) \
M(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, \
msg_rsp) \
M(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write, mcs_pn_table_write_req, \
msg_rsp) \
M(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, mcs_set_active_lmac, \
msg_rsp) \
M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \
M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \
M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, \
msg_rsp) \
M(MCS_ALLOC_CTRL_PKT_RULE, 0xa015, mcs_alloc_ctrl_pkt_rule, \
mcs_alloc_ctrl_pkt_rule_req, \
mcs_alloc_ctrl_pkt_rule_rsp) \
M(MCS_FREE_CTRL_PKT_RULE, 0xa016, mcs_free_ctrl_pkt_rule, \
mcs_free_ctrl_pkt_rule_req, msg_rsp) \
M(MCS_CTRL_PKT_RULE_WRITE, 0xa017, mcs_ctrl_pkt_rule_write, \
mcs_ctrl_pkt_rule_write_req, msg_rsp) \
M(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \
M(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp)\
M(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, \
Expand Down Expand Up @@ -1674,6 +1702,133 @@ enum mcs_direction {
MCS_TX,
};

enum mcs_rsrc_type {
MCS_RSRC_TYPE_FLOWID,
MCS_RSRC_TYPE_SECY,
MCS_RSRC_TYPE_SC,
MCS_RSRC_TYPE_SA,
};

struct mcs_alloc_rsrc_req {
struct mbox_msghdr hdr;
u8 rsrc_type;
u8 rsrc_cnt; /* Resources count */
u8 mcs_id; /* MCS block ID */
u8 dir; /* Macsec ingress or egress side */
u8 all; /* Allocate all resource type one each */
u64 rsvd;
};

struct mcs_alloc_rsrc_rsp {
struct mbox_msghdr hdr;
u8 flow_ids[128]; /* Index of reserved entries */
u8 secy_ids[128];
u8 sc_ids[128];
u8 sa_ids[256];
u8 rsrc_type;
u8 rsrc_cnt; /* No of entries reserved */
u8 mcs_id;
u8 dir;
u8 all;
u8 rsvd[256]; /* reserved fields for future expansion */
};

struct mcs_free_rsrc_req {
struct mbox_msghdr hdr;
u8 rsrc_id; /* Index of the entry to be freed */
u8 rsrc_type;
u8 mcs_id;
u8 dir;
u8 all; /* Free all the cam resources */
u64 rsvd;
};

struct mcs_flowid_entry_write_req {
struct mbox_msghdr hdr;
u64 data[4];
u64 mask[4];
u64 sci; /* CNF10K-B for tx_secy_mem_map */
u8 flow_id;
u8 secy_id; /* secyid for which flowid is mapped */
u8 sc_id; /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */
u8 ena; /* Enable tcam entry */
u8 ctrl_pkt;
u8 mcs_id;
u8 dir;
u64 rsvd;
};

struct mcs_secy_plcy_write_req {
struct mbox_msghdr hdr;
u64 plcy;
u8 secy_id;
u8 mcs_id;
u8 dir;
u64 rsvd;
};

/* RX SC_CAM mapping */
struct mcs_rx_sc_cam_write_req {
struct mbox_msghdr hdr;
u64 sci; /* SCI */
u64 secy_id; /* secy index mapped to SC */
u8 sc_id; /* SC CAM entry index */
u8 mcs_id;
u64 rsvd;
};

struct mcs_sa_plcy_write_req {
struct mbox_msghdr hdr;
u64 plcy[2][9]; /* Support 2 SA policy */
u8 sa_index[2];
u8 sa_cnt;
u8 mcs_id;
u8 dir;
u64 rsvd;
};

struct mcs_tx_sc_sa_map {
struct mbox_msghdr hdr;
u8 sa_index0;
u8 sa_index1;
u8 rekey_ena;
u8 sa_index0_vld;
u8 sa_index1_vld;
u8 tx_sa_active;
u64 sectag_sci;
u8 sc_id; /* used as index for SA_MEM_MAP */
u8 mcs_id;
u64 rsvd;
};

struct mcs_rx_sc_sa_map {
struct mbox_msghdr hdr;
u8 sa_index;
u8 sa_in_use;
u8 sc_id;
u8 an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */
u8 mcs_id;
u64 rsvd;
};

struct mcs_flowid_ena_dis_entry {
struct mbox_msghdr hdr;
u8 flow_id;
u8 ena;
u8 mcs_id;
u8 dir;
u64 rsvd;
};

struct mcs_pn_table_write_req {
struct mbox_msghdr hdr;
u64 next_pn;
u8 pn_id;
u8 mcs_id;
u8 dir;
u64 rsvd;
};

struct mcs_hw_info {
struct mbox_msghdr hdr;
u8 num_mcs_blks; /* Number of MCS blocks */
Expand Down Expand Up @@ -1762,4 +1917,60 @@ enum mcs_af_status {
MCS_AF_ERR_NOT_MAPPED = -1202,
};

struct mcs_set_pn_threshold {
struct mbox_msghdr hdr;
u64 threshold;
u8 xpn; /* '1' for setting xpn threshold */
u8 mcs_id;
u8 dir;
u64 rsvd;
};

enum mcs_ctrl_pkt_rulew_type {
MCS_CTRL_PKT_RULE_TYPE_ETH,
MCS_CTRL_PKT_RULE_TYPE_DA,
MCS_CTRL_PKT_RULE_TYPE_RANGE,
MCS_CTRL_PKT_RULE_TYPE_COMBO,
MCS_CTRL_PKT_RULE_TYPE_MAC,
};

struct mcs_alloc_ctrl_pkt_rule_req {
struct mbox_msghdr hdr;
u8 rule_type;
u8 mcs_id; /* MCS block ID */
u8 dir; /* Macsec ingress or egress side */
u64 rsvd;
};

struct mcs_alloc_ctrl_pkt_rule_rsp {
struct mbox_msghdr hdr;
u8 rule_idx;
u8 rule_type;
u8 mcs_id;
u8 dir;
u64 rsvd;
};

struct mcs_free_ctrl_pkt_rule_req {
struct mbox_msghdr hdr;
u8 rule_idx;
u8 rule_type;
u8 mcs_id;
u8 dir;
u8 all;
u64 rsvd;
};

struct mcs_ctrl_pkt_rule_write_req {
struct mbox_msghdr hdr;
u64 data0;
u64 data1;
u64 data2;
u8 rule_idx;
u8 rule_type;
u8 mcs_id;
u8 dir;
u64 rsvd;
};

#endif /* MBOX_H */
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