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MIPS: Octeon: Simplify CIU register functions.
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Collapse and simplify switch statements in functions.

Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/19713/
Cc: linux-mips@linux-mips.org
Cc: Chandrakala Chavva <cchavva@caviumnetworks.com>
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Steven J. Hill authored and Paul Burton committed Jul 3, 2018
1 parent a730c7c commit cfe1824
Showing 1 changed file with 22 additions and 94 deletions.
116 changes: 22 additions & 94 deletions arch/mips/include/asm/octeon/cvmx-ciu-defs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -42,122 +42,50 @@
#define CVMX_CIU_TIM_MULTI_CAST CVMX_CIU_ADDR(0xC200, 0, 0x00, 0)
#define CVMX_CIU_TIMX(c) CVMX_CIU_ADDR(0x0480, c, 0x0F, 8)

static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned long offset)
static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned int coreid)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070100100600ull) + (offset) * 8;
}
return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
if (cvmx_get_octeon_family() == (OCTEON_CN68XX & OCTEON_FAMILY_MASK))
return CVMX_CIU_ADDR(0x100100600, coreid, 0x0F, 8);
else
return CVMX_CIU_ADDR(0x000000680, coreid, 0x0F, 8);
}

static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned long offset)
static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned int coreid)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070100100400ull) + (offset) * 8;
}
return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
if (cvmx_get_octeon_family() == (OCTEON_CN68XX & OCTEON_FAMILY_MASK))
return CVMX_CIU_ADDR(0x100100400, coreid, 0x0F, 8);
else
return CVMX_CIU_ADDR(0x000000600, coreid, 0x0F, 8);
}

static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset)
static inline uint64_t CVMX_CIU_PP_POKEX(unsigned int coreid)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070100100200ull) + (offset) * 8;
return CVMX_CIU_ADDR(0x100100200, coreid, 0x0F, 8);
case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001010000030000ull) + (offset) * 8;
return CVMX_CIU_ADDR(0x000030000, coreid, 0x0F, 8) -
0x60000000000ull;
default:
return CVMX_CIU_ADDR(0x000000580, coreid, 0x0F, 8);
}
return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
}

static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset)
static inline uint64_t CVMX_CIU_WDOGX(unsigned int coreid)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070100100000ull) + (offset) * 8;
return CVMX_CIU_ADDR(0x100100000, coreid, 0x0F, 8);
case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001010000020000ull) + (offset) * 8;
return CVMX_CIU_ADDR(0x000020000, coreid, 0x0F, 8) -
0x60000000000ull;
default:
return CVMX_CIU_ADDR(0x000000500, coreid, 0x0F, 8);
}
return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
}


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