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Merge branch 'x86-platform-for-linus' of git://git.kernel.org/pub/scm…
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…/linux/kernel/git/tip/linux-2.6-tip

* 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (27 commits)
  x86: Clean up apic.c and apic.h
  x86: Remove superflous goal definition of tsc_sync
  x86: dt: Correct local apic documentation in device tree bindings
  x86: dt: Cleanup local apic setup
  x86: dt: Fix OLPC=y/INTEL_CE=n build
  rtc: cmos: Add OF bindings
  x86: ce4100: Use OF to setup devices
  x86: ioapic: Add OF bindings for IO_APIC
  x86: dtb: Add generic bus probe
  x86: dtb: Add support for PCI devices backed by dtb nodes
  x86: dtb: Add device tree support for HPET
  x86: dtb: Add early parsing of IO_APIC
  x86: dtb: Add irq domain abstraction
  x86: dtb: Add a device tree for CE4100
  x86: Add device tree support
  x86: e820: Remove conditional early mapping in parse_e820_ext
  x86: OLPC: Make OLPC=n build again
  x86: OLPC: Remove extra OLPC_OPENFIRMWARE_DT indirection
  x86: OLPC: Cleanup config maze completely
  x86: OLPC: Hide OLPC_OPENFIRMWARE config switch
  ...

Fix up conflicts in arch/x86/platform/ce4100/ce4100.c
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Linus Torvalds committed Mar 16, 2011
2 parents 181f977 + 25874a2 commit d109028
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93 changes: 93 additions & 0 deletions Documentation/devicetree/bindings/i2c/ce4100-i2c.txt
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CE4100 I2C
----------

CE4100 has one PCI device which is described as the I2C-Controller. This
PCI device has three PCI-bars, each bar contains a complete I2C
controller. So we have a total of three independent I2C-Controllers
which share only an interrupt line.
The driver is probed via the PCI-ID and is gathering the information of
attached devices from the devices tree.
Grant Likely recommended to use the ranges property to map the PCI-Bar
number to its physical address and to use this to find the child nodes
of the specific I2C controller. This were his exact words:

Here's where the magic happens. Each entry in
ranges describes how the parent pci address space
(middle group of 3) is translated to the local
address space (first group of 2) and the size of
each range (last cell). In this particular case,
the first cell of the local address is chosen to be
1:1 mapped to the BARs, and the second is the
offset from be base of the BAR (which would be
non-zero if you had 2 or more devices mapped off
the same BAR)

ranges allows the address mapping to be described
in a way that the OS can interpret without
requiring custom device driver code.

This is an example which is used on FalconFalls:
------------------------------------------------
i2c-controller@b,2 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "pci8086,2e68.2",
"pci8086,2e68",
"pciclass,ff0000",
"pciclass,ff00";

reg = <0x15a00 0x0 0x0 0x0 0x0>;
interrupts = <16 1>;

/* as described by Grant, the first number in the group of
* three is the bar number followed by the 64bit bar address
* followed by size of the mapping. The bar address
* requires also a valid translation in parents ranges
* property.
*/
ranges = <0 0 0x02000000 0 0xdffe0500 0x100
1 0 0x02000000 0 0xdffe0600 0x100
2 0 0x02000000 0 0xdffe0700 0x100>;

i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ce4100-i2c-controller";

/* The first number in the reg property is the
* number of the bar
*/
reg = <0 0 0x100>;

/* This I2C controller has no devices */
};

i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ce4100-i2c-controller";
reg = <1 0 0x100>;

/* This I2C controller has one gpio controller */
gpio@26 {
#gpio-cells = <2>;
compatible = "ti,pcf8575";
reg = <0x26>;
gpio-controller;
};
};

i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ce4100-i2c-controller";
reg = <2 0 0x100>;

gpio@26 {
#gpio-cells = <2>;
compatible = "ti,pcf8575";
reg = <0x26>;
gpio-controller;
};
};
};
28 changes: 28 additions & 0 deletions Documentation/devicetree/bindings/rtc/rtc-cmos.txt
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Motorola mc146818 compatible RTC
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Required properties:
- compatible : "motorola,mc146818"
- reg : should contain registers location and length.

Optional properties:
- interrupts : should contain interrupt.
- interrupt-parent : interrupt source phandle.
- ctrl-reg : Contains the initial value of the control register also
called "Register B".
- freq-reg : Contains the initial value of the frequency register also
called "Regsiter A".

"Register A" and "B" are usually initialized by the firmware (BIOS for
instance). If this is not done, it can be performed by the driver.

ISA Example:

rtc@70 {
compatible = "motorola,mc146818";
interrupts = <8 3>;
interrupt-parent = <&ioapic1>;
ctrl-reg = <2>;
freq-reg = <0x26>;
reg = <1 0x70 2>;
};
38 changes: 38 additions & 0 deletions Documentation/devicetree/bindings/x86/ce4100.txt
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CE4100 Device Tree Bindings
---------------------------

The CE4100 SoC uses for in core peripherals the following compatible
format: <vendor>,<chip>-<device>.
Many of the "generic" devices like HPET or IO APIC have the ce4100
name in their compatible property because they first appeared in this
SoC.

The CPU node
------------
cpu@0 {
device_type = "cpu";
compatible = "intel,ce4100";
reg = <0>;
lapic = <&lapic0>;
};

The reg property describes the CPU number. The lapic property points to
the local APIC timer.

The SoC node
------------

This node describes the in-core peripherals. Required property:
compatible = "intel,ce4100-cp";

The PCI node
------------
This node describes the PCI bus on the SoC. Its property should be
compatible = "intel,ce4100-pci", "pci";

If the OS is using the IO-APIC for interrupt routing then the reported
interrupt numbers for devices is no longer true. In order to obtain the
correct interrupt number, the child node which represents the device has
to contain the interrupt property. Besides the interrupt property it has
to contain at least the reg property containing the PCI bus address and
compatible property according to "PCI Bus Binding Revision 2.1".
26 changes: 26 additions & 0 deletions Documentation/devicetree/bindings/x86/interrupt.txt
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Interrupt chips
---------------

* Intel I/O Advanced Programmable Interrupt Controller (IO APIC)

Required properties:
--------------------
compatible = "intel,ce4100-ioapic";
#interrupt-cells = <2>;

Device's interrupt property:

interrupts = <P S>;

The first number (P) represents the interrupt pin which is wired to the
IO APIC. The second number (S) represents the sense of interrupt which
should be configured and can be one of:
0 - Edge Rising
1 - Level Low
2 - Level High
3 - Edge Falling

* Local APIC
Required property:

compatible = "intel,ce4100-lapic";
6 changes: 6 additions & 0 deletions Documentation/devicetree/bindings/x86/timer.txt
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@@ -0,0 +1,6 @@
Timers
------

* High Precision Event Timer (HPET)
Required property:
compatible = "intel,ce4100-hpet";
20 changes: 20 additions & 0 deletions Documentation/devicetree/booting-without-of.txt
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@ Table of Contents

I - Introduction
1) Entry point for arch/powerpc
2) Entry point for arch/x86

II - The DT block format
1) Header
Expand Down Expand Up @@ -225,6 +226,25 @@ it with special cases.
cannot support both configurations with Book E and configurations
with classic Powerpc architectures.

2) Entry point for arch/x86
-------------------------------

There is one single 32bit entry point to the kernel at code32_start,
the decompressor (the real mode entry point goes to the same 32bit
entry point once it switched into protected mode). That entry point
supports one calling convention which is documented in
Documentation/x86/boot.txt
The physical pointer to the device-tree block (defined in chapter II)
is passed via setup_data which requires at least boot protocol 2.09.
The type filed is defined as

#define SETUP_DTB 2

This device-tree is used as an extension to the "boot page". As such it
does not parse / consider data which is already covered by the boot
page. This includes memory size, reserved ranges, command line arguments
or initrd address. It simply holds information which can not be retrieved
otherwise like interrupt routing or a list of devices behind an I2C bus.

II - The DT block format
========================
Expand Down
12 changes: 12 additions & 0 deletions arch/microblaze/include/asm/pci-bridge.h
Original file line number Diff line number Diff line change
Expand Up @@ -104,18 +104,30 @@ struct pci_controller {
int global_number; /* PCI domain number */
};

#ifdef CONFIG_PCI
static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
{
return bus->sysdata;
}

static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
{
struct pci_controller *host;

if (bus->self)
return pci_device_to_OF_node(bus->self);
host = pci_bus_to_host(bus);
return host ? host->dn : NULL;
}

static inline int isa_vaddr_is_ioport(void __iomem *address)
{
/* No specific ISA handling on ppc32 at this stage, it
* all goes through PCI
*/
return 0;
}
#endif /* CONFIG_PCI */

/* These are used for config access before all the PCI probing
has been done. */
Expand Down
15 changes: 0 additions & 15 deletions arch/microblaze/include/asm/prom.h
Original file line number Diff line number Diff line change
Expand Up @@ -64,21 +64,6 @@ extern void kdump_move_device_tree(void);
/* CPU OF node matching */
struct device_node *of_get_cpu_node(int cpu, unsigned int *thread);

/**
* of_irq_map_pci - Resolve the interrupt for a PCI device
* @pdev: the device whose interrupt is to be resolved
* @out_irq: structure of_irq filled by this function
*
* This function resolves the PCI interrupt for a given PCI device. If a
* device-node exists for a given pci_dev, it will use normal OF tree
* walking. If not, it will implement standard swizzling and walk up the
* PCI tree until an device-node is found, at which point it will finish
* resolving using the OF tree walking.
*/
struct pci_dev;
struct of_irq;
extern int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq);

#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */

Expand Down
77 changes: 0 additions & 77 deletions arch/microblaze/kernel/prom_parse.c
Original file line number Diff line number Diff line change
Expand Up @@ -2,88 +2,11 @@

#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/pci_regs.h>
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/etherdevice.h>
#include <linux/of_address.h>
#include <asm/prom.h>
#include <asm/pci-bridge.h>

#ifdef CONFIG_PCI
int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq)
{
struct device_node *dn, *ppnode;
struct pci_dev *ppdev;
u32 lspec;
u32 laddr[3];
u8 pin;
int rc;

/* Check if we have a device node, if yes, fallback to standard OF
* parsing
*/
dn = pci_device_to_OF_node(pdev);
if (dn)
return of_irq_map_one(dn, 0, out_irq);

/* Ok, we don't, time to have fun. Let's start by building up an
* interrupt spec. we assume #interrupt-cells is 1, which is standard
* for PCI. If you do different, then don't use that routine.
*/
rc = pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &pin);
if (rc != 0)
return rc;
/* No pin, exit */
if (pin == 0)
return -ENODEV;

/* Now we walk up the PCI tree */
lspec = pin;
for (;;) {
/* Get the pci_dev of our parent */
ppdev = pdev->bus->self;

/* Ouch, it's a host bridge... */
if (ppdev == NULL) {
struct pci_controller *host;
host = pci_bus_to_host(pdev->bus);
ppnode = host ? host->dn : NULL;
/* No node for host bridge ? give up */
if (ppnode == NULL)
return -EINVAL;
} else
/* We found a P2P bridge, check if it has a node */
ppnode = pci_device_to_OF_node(ppdev);

/* Ok, we have found a parent with a device-node, hand over to
* the OF parsing code.
* We build a unit address from the linux device to be used for
* resolution. Note that we use the linux bus number which may
* not match your firmware bus numbering.
* Fortunately, in most cases, interrupt-map-mask doesn't
* include the bus number as part of the matching.
* You should still be careful about that though if you intend
* to rely on this function (you ship a firmware that doesn't
* create device nodes for all PCI devices).
*/
if (ppnode)
break;

/* We can only get here if we hit a P2P bridge with no node,
* let's do standard swizzling and try again
*/
lspec = pci_swizzle_interrupt_pin(pdev, lspec);
pdev = ppdev;
}

laddr[0] = (pdev->bus->number << 16)
| (pdev->devfn << 8);
laddr[1] = laddr[2] = 0;
return of_irq_map_raw(ppnode, &lspec, 1, laddr, out_irq);
}
EXPORT_SYMBOL_GPL(of_irq_map_pci);
#endif /* CONFIG_PCI */

void of_parse_dma_window(struct device_node *dn, const void *dma_window_prop,
unsigned long *busno, unsigned long *phys, unsigned long *size)
Expand Down
1 change: 1 addition & 0 deletions arch/microblaze/pci/pci-common.c
Original file line number Diff line number Diff line change
Expand Up @@ -29,6 +29,7 @@
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_pci.h>

#include <asm/processor.h>
#include <asm/io.h>
Expand Down
10 changes: 10 additions & 0 deletions arch/powerpc/include/asm/pci-bridge.h
Original file line number Diff line number Diff line change
Expand Up @@ -171,6 +171,16 @@ static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
return bus->sysdata;
}

static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
{
struct pci_controller *host;

if (bus->self)
return pci_device_to_OF_node(bus->self);
host = pci_bus_to_host(bus);
return host ? host->dn : NULL;
}

static inline int isa_vaddr_is_ioport(void __iomem *address)
{
/* No specific ISA handling on ppc32 at this stage, it
Expand Down
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