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Merge tag 'pinctrl-v4.14-1' of git://git.kernel.org/pub/scm/linux/ker…
…nel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the big bulk of pin control changes for the v4.14 kernel.
There are just a few bigger changes (new drivers mostly) and then a
lot of small patches all over the place.
Core changes:
- Decision to wrap the sleep mode of the Spreadtrum and in the future
others into a specially tagged state. The generic DT bindings and
the new Spreadtrum driver conforms to this. Others should be moved
over if possible.
New drivers:
- Spreadtrum SoCs especially the SC9860 SoC.
- Storlink/Cortina Gemini 3512 and 3516 SoCs.
New subdrivers:
- Intel Denverton subdriver.
- Intel Cannon Lake subdriver.
- Intel Lewisburg subdriver.
- Allwinner sunxi: R40 subdriver for A10.
- Socionext uniphier PXs3 subdriver.
- Rockchip RK3128 subdriver.
- Renesas SH-PFC R8A77995 subdriver.
Miscellaneous:
- Qualcomm APQ8064 can handle general purpose clock muxing.
- Mediatek MT7623 PCIe mux data fixed up.
- Intel GPIO IRQs are disabled during suspend.
- Several fixes and addtions to Renesas r8a7796.
- Qualcomm SPMI GPIO supports dtest route and LV/MV subtype.
- Input schmitt trigger support in Rockchip RV1108.
- Aspeed G4 and G5 USB host/device pin control control added.
- Qualcomm IPQ4019 has matured with a few missing pin groups and
control bits put in place.
- Lots of constification, this is the latest in cocinelle fixes"
* tag 'pinctrl-v4.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (147 commits)
Revert "pinctrl: sunxi: Don't enforce bias disable (for now)"
pinctrl: uniphier: fix members of rmii group for Pro4
pinctrl: Delete an error message
pinctrl: core: Delete an error message
pinctrl: intel: Read back TX buffer state
pinctrl: rockchip: Add rv1108 recalculated iomux support
pinctrl: intel: Decrease indentation in intel_gpio_set()
pinctrl: rza1: Remove suffix from gpiochip label
pinctrl: qcom: spmi-gpio: Correct power_source range check
pinctrl: freescale: make mxs_regs const
pinctrl: aspeed: Rework strap register write logic for the AST2500
pinctrl: rza1: off by one in rza1_parse_gpiochip()
pinctrl: qcom: General Purpose clocks for apq8064
pinctrl: sprd: Add Spreadtrum pin control driver
dt-bindings: pinctrl: Add DT bindings for Spreadtrum SC9860
pinctrl: Add sleep related state to indicate sleep related configs
pinctrl: mediatek: update PCIe mux data for MT7623
pinctrl: intel: Add Intel Lewisburg GPIO support
pinctrl: intel: Add Intel Cannon Lake PCH-H pin controller support
pinctrl: aspeed: Fix ast2500 strap register write logic
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59
Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,59 @@ | ||
| Cortina Systems Gemini pin controller | ||
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||
| This pin controller is found in the Cortina Systems Gemini SoC family, | ||
| see further arm/gemini.txt. It is a purely group-based multiplexing pin | ||
| controller. | ||
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| The pin controller node must be a subnode of the system controller node. | ||
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| Required properties: | ||
| - compatible: "cortina,gemini-pinctrl" | ||
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| Subnodes of the pin controller contain pin control multiplexing set-up. | ||
| Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes. | ||
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| Example: | ||
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| syscon { | ||
| compatible = "cortina,gemini-syscon"; | ||
| ... | ||
| pinctrl { | ||
| compatible = "cortina,gemini-pinctrl"; | ||
| pinctrl-names = "default"; | ||
| pinctrl-0 = <&dram_default_pins>, <&system_default_pins>, | ||
| <&vcontrol_default_pins>; | ||
|
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| dram_default_pins: pinctrl-dram { | ||
| mux { | ||
| function = "dram"; | ||
| groups = "dramgrp"; | ||
| }; | ||
| }; | ||
| rtc_default_pins: pinctrl-rtc { | ||
| mux { | ||
| function = "rtc"; | ||
| groups = "rtcgrp"; | ||
| }; | ||
| }; | ||
| power_default_pins: pinctrl-power { | ||
| mux { | ||
| function = "power"; | ||
| groups = "powergrp"; | ||
| }; | ||
| }; | ||
| system_default_pins: pinctrl-system { | ||
| mux { | ||
| function = "system"; | ||
| groups = "systemgrp"; | ||
| }; | ||
| }; | ||
| (...) | ||
| uart_default_pins: pinctrl-uart { | ||
| mux { | ||
| function = "uart"; | ||
| groups = "uartrxtxgrp"; | ||
| }; | ||
| }; | ||
| }; | ||
| }; |
61 changes: 61 additions & 0 deletions
61
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt
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| * Freescale i.MX7ULP IOMUX Controller | ||
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| i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 | ||
| ports and IOMUXC DDR for DDR interface. | ||
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| Note: | ||
| This binding doc is only for the IOMUXC1 support in A7 Domain and it only | ||
| supports generic pin config. | ||
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| Please also refer pinctrl-bindings.txt in this directory for generic pinctrl | ||
| binding. | ||
|
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| === Pin Controller Node === | ||
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| Required properties: | ||
| - compatible: "fsl,imx7ulp-iomuxc1" | ||
| - reg: Should contain the base physical address and size of the iomuxc | ||
| registers. | ||
|
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||
| === Pin Configuration Node === | ||
| - pinmux: One integers array, represents a group of pins mux setting. | ||
| The format is pinmux = <PIN_FUNC_ID>, PIN_FUNC_ID is a pin working on | ||
| a specific function. | ||
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| NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux | ||
| and config register as follows: | ||
| <mux_conf_reg input_reg mux_mode input_val> | ||
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| Refer to imx7ulp-pinfunc.h in in device tree source folder for all | ||
| available imx7ulp PIN_FUNC_ID. | ||
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| Optional Properties: | ||
| - drive-strength Integer. Controls Drive Strength | ||
| 0: Standard | ||
| 1: Hi Driver | ||
| - drive-push-pull Bool. Enable Pin Push-pull | ||
| - drive-open-drain Bool. Enable Pin Open-drian | ||
| - slew-rate: Integer. Controls Slew Rate | ||
| 0: Standard | ||
| 1: Slow | ||
| - bias-disable: Bool. Pull disabled | ||
| - bias-pull-down: Bool. Pull down on pin | ||
| - bias-pull-up: Bool. Pull up on pin | ||
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| Examples: | ||
| #include "imx7ulp-pinfunc.h" | ||
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| /* Pin Controller Node */ | ||
| iomuxc1: iomuxc@40ac0000 { | ||
| compatible = "fsl,imx7ulp-iomuxc1"; | ||
| reg = <0x40ac0000 0x1000>; | ||
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| /* Pin Configuration Node */ | ||
| pinctrl_lpuart4: lpuart4grp { | ||
| pinmux = < | ||
| IMX7ULP_PAD_PTC3__LPUART4_RX | ||
| IMX7ULP_PAD_PTC2__LPUART4_TX | ||
| >; | ||
| bias-pull-up; | ||
| }; | ||
| }; |
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83 changes: 83 additions & 0 deletions
83
Documentation/devicetree/bindings/pinctrl/sprd,pinctrl.txt
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| * Spreadtrum Pin Controller | ||
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| The Spreadtrum pin controller are organized in 3 blocks (types). | ||
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| The first block comprises some global control registers, and each | ||
| register contains several bit fields with one bit or several bits | ||
| to configure for some global common configuration, such as domain | ||
| pad driving level, system control select and so on ("domain pad | ||
| driving level": One pin can output 3.0v or 1.8v, depending on the | ||
| related domain pad driving selection, if the related domain pad | ||
| slect 3.0v, then the pin can output 3.0v. "system control" is used | ||
| to choose one function (like: UART0) for which system, since we | ||
| have several systems (AP/CP/CM4) on one SoC.). | ||
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| There are too much various configuration that we can not list all | ||
| of them, so we can not make every Spreadtrum-special configuration | ||
| as one generic configuration, and maybe it will add more strange | ||
| global configuration in future. Then we add one "sprd,control" to | ||
| set these various global control configuration, and we need use | ||
| magic number for this property. | ||
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| Moreover we recognise every fields comprising one bit or several | ||
| bits in one global control register as one pin, thus we should | ||
| record every pin's bit offset, bit width and register offset to | ||
| configure this field (pin). | ||
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| The second block comprises some common registers which have unified | ||
| register definition, and each register described one pin is used | ||
| to configure the pin sleep mode, function select and sleep related | ||
| configuration. | ||
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| Now we have 4 systems for sleep mode on SC9860 SoC: AP system, | ||
| PUBCP system, TGLDSP system and AGDSP system. And the pin sleep | ||
| related configuration are: | ||
| - input-enable | ||
| - input-disable | ||
| - output-high | ||
| - output-low | ||
| - bias-pull-up | ||
| - bias-pull-down | ||
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| In some situation we need set the pin sleep mode and pin sleep related | ||
| configuration, to set the pin sleep related configuration automatically | ||
| by hardware when the system specified by sleep mode goes into deep | ||
| sleep mode. For example, if we set the pin sleep mode as PUBCP_SLEEP | ||
| and set the pin sleep related configuration as "input-enable", which | ||
| means when PUBCP system goes into deep sleep mode, this pin will be set | ||
| input enable automatically. | ||
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| Moreover we can not use the "sleep" state, since some systems (like: | ||
| PUBCP system) do not run linux kernel OS (only AP system run linux | ||
| kernel on SC9860 platform), then we can not select "sleep" state | ||
| when the PUBCP system goes into deep sleep mode. Thus we introduce | ||
| "sprd,sleep-mode" property to set pin sleep mode. | ||
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| The last block comprises some misc registers which also have unified | ||
| register definition, and each register described one pin is used to | ||
| configure drive strength, pull up/down and so on. Especially for pull | ||
| up, we have two kind pull up resistor: 20K and 4.7K. | ||
|
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| Required properties for Spreadtrum pin controller: | ||
| - compatible: "sprd,<soc>-pinctrl" | ||
| Please refer to each sprd,<soc>-pinctrl.txt binding doc for supported SoCs. | ||
| - reg: The register address of pin controller device. | ||
| - pins : An array of pin names. | ||
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| Optional properties: | ||
| - function: Specified the function name. | ||
| - drive-strength: Drive strength in mA. | ||
| - input-schmitt-disable: Enable schmitt-trigger mode. | ||
| - input-schmitt-enable: Disable schmitt-trigger mode. | ||
| - bias-disable: Disable pin bias. | ||
| - bias-pull-down: Pull down on pin. | ||
| - bias-pull-up: Pull up on pin. | ||
| - input-enable: Enable pin input. | ||
| - input-disable: Enable pin output. | ||
| - output-high: Set the pin as an output level high. | ||
| - output-low: Set the pin as an output level low. | ||
| - sleep-hardware-state: Indicate these configs in this state are sleep related. | ||
| - sprd,control: Control values referring to databook for global control pins. | ||
| - sprd,sleep-mode: Sleep mode selection. | ||
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| Please refer to each sprd,<soc>-pinctrl.txt binding doc for supported values. |
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