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Merge branches 'clk-mvebu-spdx', 'clk-meson', 'clk-imx7d-mu', 'clk-im…
…x-init-array-cleanup' and 'clk-rockchip' into clk-next * clk-mvebu-spdx: clk: mvebu: armada-37xx-periph: switch to SPDX license identifier * clk-meson: clk: meson: add gen_clk clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition clk: meson-axg: add clocks required by pcie driver clk: meson: remove unused clk-audio-divider driver clk: meson: stop rate propagation for audio clocks clk: meson: axg: add the audio clock controller driver clk: meson: add axg audio sclk divider driver clk: meson: add triple phase clock driver clk: meson: add clk-phase clock driver clk: meson: clean-up meson clock configuration clk: meson: remove obsolete register access clk: meson: expose GEN_CLK clkid clk: meson-axg: add pcie and mipi clock bindings dt-bindings: clock: add meson axg audio clock controller bindings clk: meson: audio-divider is one based clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL * clk-imx7d-mu: : - i.MX7D mailbox clk support clk: imx7d: add IMX7D_MU_ROOT_CLK * clk-imx-init-array-cleanup: : - i.MX clk init arrays removed in place of CLK_IS_CRITICAL clk: imx6sx: remove clks_init_on array clk: imx6sl: remove clks_init_on array clk: imx6q: remove clks_init_on array * clk-rockchip: clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399 clk: rockchip: fix clk_i2sout parent selection bits on rk3399 clk: rockchip: add clock controller for px30 clk: rockchip: add support for half divider dt-bindings: add bindings for px30 clock controller clk: rockchip: add dt-binding header for px30
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56
Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
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| @@ -0,0 +1,56 @@ | ||
| * Amlogic AXG Audio Clock Controllers | ||
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||
| The Amlogic AXG audio clock controller generates and supplies clock to the | ||
| other elements of the audio subsystem, such as fifos, i2s, spdif and pdm | ||
| devices. | ||
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| Required Properties: | ||
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| - compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D | ||
| - reg : physical base address of the clock controller and length of | ||
| memory mapped region. | ||
| - clocks : a list of phandle + clock-specifier pairs for the clocks listed | ||
| in clock-names. | ||
| - clock-names : must contain the following: | ||
| * "pclk" - Main peripheral bus clock | ||
| may contain the following: | ||
| * "mst_in[0-7]" - 8 input plls to generate clock signals | ||
| * "slv_sclk[0-9]" - 10 slave bit clocks provided by external | ||
| components. | ||
| * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external | ||
| components. | ||
| - resets : phandle of the internal reset line | ||
| - #clock-cells : should be 1. | ||
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| Each clock is assigned an identifier and client nodes can use this identifier | ||
| to specify the clock which they consume. All available clocks are defined as | ||
| preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be | ||
| used in device tree sources. | ||
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| Example: | ||
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| clkc_audio: clock-controller@0 { | ||
| compatible = "amlogic,axg-audio-clkc"; | ||
| reg = <0x0 0x0 0x0 0xb4>; | ||
| #clock-cells = <1>; | ||
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| clocks = <&clkc CLKID_AUDIO>, | ||
| <&clkc CLKID_MPLL0>, | ||
| <&clkc CLKID_MPLL1>, | ||
| <&clkc CLKID_MPLL2>, | ||
| <&clkc CLKID_MPLL3>, | ||
| <&clkc CLKID_HIFI_PLL>, | ||
| <&clkc CLKID_FCLK_DIV3>, | ||
| <&clkc CLKID_FCLK_DIV4>, | ||
| <&clkc CLKID_GP0_PLL>; | ||
| clock-names = "pclk", | ||
| "mst_in0", | ||
| "mst_in1", | ||
| "mst_in2", | ||
| "mst_in3", | ||
| "mst_in4", | ||
| "mst_in5", | ||
| "mst_in6", | ||
| "mst_in7"; | ||
| resets = <&reset RESET_AUDIO>; | ||
| }; |
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65
Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt
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| * Rockchip PX30 Clock and Reset Unit | ||
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| The PX30 clock controller generates and supplies clock to various | ||
| controllers within the SoC and also implements a reset controller for SoC | ||
| peripherals. | ||
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| Required Properties: | ||
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| - compatible: PMU for CRU should be "rockchip,px30-pmu-cru" | ||
| - compatible: CRU should be "rockchip,px30-cru" | ||
| - reg: physical base address of the controller and length of memory mapped | ||
| region. | ||
| - #clock-cells: should be 1. | ||
| - #reset-cells: should be 1. | ||
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| Optional Properties: | ||
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| - rockchip,grf: phandle to the syscon managing the "general register files" | ||
| If missing, pll rates are not changeable, due to the missing pll lock status. | ||
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| Each clock is assigned an identifier and client nodes can use this identifier | ||
| to specify the clock which they consume. All available clocks are defined as | ||
| preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be | ||
| used in device tree sources. Similar macros exist for the reset sources in | ||
| these files. | ||
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| External clocks: | ||
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| There are several clocks that are generated outside the SoC. It is expected | ||
| that they are defined using standard clock bindings with following | ||
| clock-output-names: | ||
| - "xin24m" - crystal input - required, | ||
| - "xin32k" - rtc clock - optional, | ||
| - "i2sx_clkin" - external I2S clock - optional, | ||
| - "gmac_clkin" - external GMAC clock - optional | ||
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| Example: Clock controller node: | ||
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| pmucru: clock-controller@ff2bc000 { | ||
| compatible = "rockchip,px30-pmucru"; | ||
| reg = <0x0 0xff2bc000 0x0 0x1000>; | ||
| #clock-cells = <1>; | ||
| #reset-cells = <1>; | ||
| }; | ||
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| cru: clock-controller@ff2b0000 { | ||
| compatible = "rockchip,px30-cru"; | ||
| reg = <0x0 0xff2b0000 0x0 0x1000>; | ||
| rockchip,grf = <&grf>; | ||
| #clock-cells = <1>; | ||
| #reset-cells = <1>; | ||
| }; | ||
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| Example: UART controller node that consumes the clock generated by the clock | ||
| controller: | ||
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| uart0: serial@ff030000 { | ||
| compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; | ||
| reg = <0x0 0xff030000 0x0 0x100>; | ||
| interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | ||
| clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; | ||
| clock-names = "baudclk", "apb_pclk"; | ||
| reg-shift = <2>; | ||
| reg-io-width = <4>; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,46 +1,56 @@ | ||
| config COMMON_CLK_AMLOGIC | ||
| bool | ||
| depends on OF | ||
| depends on ARCH_MESON || COMPILE_TEST | ||
| select COMMON_CLK_REGMAP_MESON | ||
|
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| config COMMON_CLK_AMLOGIC_AUDIO | ||
| bool | ||
| depends on ARCH_MESON || COMPILE_TEST | ||
| select COMMON_CLK_AMLOGIC | ||
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| config COMMON_CLK_MESON_AO | ||
| bool | ||
| depends on OF | ||
| depends on ARCH_MESON || COMPILE_TEST | ||
| select COMMON_CLK_REGMAP_MESON | ||
| select RESET_CONTROLLER | ||
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| config COMMON_CLK_REGMAP_MESON | ||
| bool | ||
| select REGMAP | ||
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| config COMMON_CLK_MESON8B | ||
| bool | ||
| depends on COMMON_CLK_AMLOGIC | ||
| select COMMON_CLK_AMLOGIC | ||
| select RESET_CONTROLLER | ||
| select COMMON_CLK_REGMAP_MESON | ||
| help | ||
| Support for the clock controller on AmLogic S802 (Meson8), | ||
| S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you | ||
| want peripherals and CPU frequency scaling to work. | ||
|
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| config COMMON_CLK_GXBB | ||
| bool | ||
| depends on COMMON_CLK_AMLOGIC | ||
| select RESET_CONTROLLER | ||
| select COMMON_CLK_AMLOGIC | ||
| select COMMON_CLK_MESON_AO | ||
| select COMMON_CLK_REGMAP_MESON | ||
| select MFD_SYSCON | ||
| help | ||
| Support for the clock controller on AmLogic S905 devices, aka gxbb. | ||
| Say Y if you want peripherals and CPU frequency scaling to work. | ||
|
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| config COMMON_CLK_AXG | ||
| bool | ||
| depends on COMMON_CLK_AMLOGIC | ||
| select RESET_CONTROLLER | ||
| select COMMON_CLK_AMLOGIC | ||
| select COMMON_CLK_MESON_AO | ||
| select COMMON_CLK_REGMAP_MESON | ||
| select MFD_SYSCON | ||
| help | ||
| Support for the clock controller on AmLogic A113D devices, aka axg. | ||
| Say Y if you want peripherals and CPU frequency scaling to work. | ||
|
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| config COMMON_CLK_AXG_AUDIO | ||
| tristate "Meson AXG Audio Clock Controller Driver" | ||
| depends on COMMON_CLK_AXG | ||
| select COMMON_CLK_AMLOGIC_AUDIO | ||
| select MFD_SYSCON | ||
| help | ||
| Support for the audio clock controller on AmLogic A113D devices, | ||
| aka axg, Say Y if you want audio subsystem to work. |
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