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ARM: at91: make rm9200 rtc drivers soc independent
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switch the rtc drivers to resource and pass it via platform_device

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
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Jean-Christophe PLAGNIOL-VILLARD committed Nov 28, 2011
1 parent be6d432 commit d28bdfc
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Showing 7 changed files with 108 additions and 55 deletions.
16 changes: 15 additions & 1 deletion arch/arm/mach-at91/at91rm9200_devices.c
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Expand Up @@ -665,10 +665,24 @@ static void __init at91_add_device_tc(void) { }
* -------------------------------------------------------------------- */

#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
static struct resource rtc_resources[] = {
[0] = {
.start = AT91RM9200_BASE_RTC,
.end = AT91RM9200_BASE_RTC + SZ_256 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AT91_ID_SYS,
.end = AT91_ID_SYS,
.flags = IORESOURCE_IRQ,
},
};

static struct platform_device at91rm9200_rtc_device = {
.name = "at91_rtc",
.id = -1,
.num_resources = 0,
.resource = rtc_resources,
.num_resources = ARRAY_SIZE(rtc_resources),
};

static void __init at91_add_device_rtc(void)
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16 changes: 15 additions & 1 deletion arch/arm/mach-at91/at91sam9g45_devices.c
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Expand Up @@ -1009,10 +1009,24 @@ static void __init at91_add_device_tc(void) { }
* -------------------------------------------------------------------- */

#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
static struct resource rtc_resources[] = {
[0] = {
.start = AT91SAM9G45_BASE_RTC,
.end = AT91SAM9G45_BASE_RTC + SZ_256 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AT91_ID_SYS,
.end = AT91_ID_SYS,
.flags = IORESOURCE_IRQ,
},
};

static struct platform_device at91sam9g45_rtc_device = {
.name = "at91_rtc",
.id = -1,
.num_resources = 0,
.resource = rtc_resources,
.num_resources = ARRAY_SIZE(rtc_resources),
};

static void __init at91_add_device_rtc(void)
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24 changes: 12 additions & 12 deletions arch/arm/mach-at91/include/mach/at91_rtc.h
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Expand Up @@ -16,7 +16,7 @@
#ifndef AT91_RTC_H
#define AT91_RTC_H

#define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */
#define AT91_RTC_CR 0x00 /* Control Register */
#define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */
#define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */
#define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */
Expand All @@ -29,44 +29,44 @@
#define AT91_RTC_CALEVSEL_MONTH (1 << 16)
#define AT91_RTC_CALEVSEL_YEAR (2 << 16)

#define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */
#define AT91_RTC_MR 0x04 /* Mode Register */
#define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */

#define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */
#define AT91_RTC_TIMR 0x08 /* Time Register */
#define AT91_RTC_SEC (0x7f << 0) /* Current Second */
#define AT91_RTC_MIN (0x7f << 8) /* Current Minute */
#define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */
#define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */

#define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */
#define AT91_RTC_CALR 0x0c /* Calendar Register */
#define AT91_RTC_CENT (0x7f << 0) /* Current Century */
#define AT91_RTC_YEAR (0xff << 8) /* Current Year */
#define AT91_RTC_MONTH (0x1f << 16) /* Current Month */
#define AT91_RTC_DAY (7 << 21) /* Current Day */
#define AT91_RTC_DATE (0x3f << 24) /* Current Date */

#define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */
#define AT91_RTC_TIMALR 0x10 /* Time Alarm Register */
#define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */
#define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */
#define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */

#define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */
#define AT91_RTC_CALALR 0x14 /* Calendar Alarm Register */
#define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */
#define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */

#define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */
#define AT91_RTC_SR 0x18 /* Status Register */
#define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */
#define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */
#define AT91_RTC_SECEV (1 << 2) /* Second Event */
#define AT91_RTC_TIMEV (1 << 3) /* Time Event */
#define AT91_RTC_CALEV (1 << 4) /* Calendar Event */

#define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */
#define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */
#define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */
#define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */
#define AT91_RTC_SCCR 0x1c /* Status Clear Command Register */
#define AT91_RTC_IER 0x20 /* Interrupt Enable Register */
#define AT91_RTC_IDR 0x24 /* Interrupt Disable Register */
#define AT91_RTC_IMR 0x28 /* Interrupt Mask Register */

#define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */
#define AT91_RTC_VER 0x2c /* Valid Entry Register */
#define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */
#define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */
#define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */
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2 changes: 1 addition & 1 deletion arch/arm/mach-at91/include/mach/at91rm9200.h
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Expand Up @@ -81,14 +81,14 @@
*/
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */
#define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */
#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */
#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */

#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */
#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */
#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */
#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */
#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */
#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */

#define AT91_USART0 AT91RM9200_BASE_US0
#define AT91_USART1 AT91RM9200_BASE_US1
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2 changes: 1 addition & 1 deletion arch/arm/mach-at91/include/mach/at91sam9g45.h
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Expand Up @@ -92,7 +92,6 @@
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS)

#define AT91SAM9G45_BASE_ECC 0xffffe200
#define AT91SAM9G45_BASE_DMA 0xffffec00
Expand All @@ -107,6 +106,7 @@
#define AT91SAM9G45_BASE_RTT 0xfffffd20
#define AT91SAM9G45_BASE_PIT 0xfffffd30
#define AT91SAM9G45_BASE_WDT 0xfffffd40
#define AT91SAM9G45_BASE_RTC 0xfffffdb0

#define AT91_USART0 AT91SAM9G45_BASE_US0
#define AT91_USART1 AT91SAM9G45_BASE_US1
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2 changes: 1 addition & 1 deletion arch/arm/mach-at91/include/mach/at91sam9rl.h
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Expand Up @@ -75,7 +75,6 @@
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS)

#define AT91SAM9RL_BASE_DMA 0xffffe600
#define AT91SAM9RL_BASE_ECC 0xffffe800
Expand All @@ -89,6 +88,7 @@
#define AT91SAM9RL_BASE_RTT 0xfffffd20
#define AT91SAM9RL_BASE_PIT 0xfffffd30
#define AT91SAM9RL_BASE_WDT 0xfffffd40
#define AT91SAM9RL_BASE_RTC 0xfffffe00

#define AT91_USART0 AT91SAM9RL_BASE_US0
#define AT91_USART1 AT91SAM9RL_BASE_US1
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