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Merge tag 'v5.2-rc6' into sched/core, to refresh the branch
Signed-off-by: Ingo Molnar <mingo@kernel.org>
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,168 @@ | ||
| # SPDX-License-Identifier: (GPL-2.0 OR MIT) | ||
| %YAML 1.2 | ||
| --- | ||
| $id: http://devicetree.org/schemas/riscv/cpus.yaml# | ||
| $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
|
|
||
| title: RISC-V bindings for 'cpus' DT nodes | ||
|
|
||
| maintainers: | ||
| - Paul Walmsley <paul.walmsley@sifive.com> | ||
| - Palmer Dabbelt <palmer@sifive.com> | ||
|
|
||
| allOf: | ||
| - $ref: /schemas/cpus.yaml# | ||
|
|
||
| properties: | ||
| $nodename: | ||
| const: cpus | ||
| description: Container of cpu nodes | ||
|
|
||
| '#address-cells': | ||
| const: 1 | ||
| description: | | ||
| A single unsigned 32-bit integer uniquely identifies each RISC-V | ||
| hart in a system. (See the "reg" node under the "cpu" node, | ||
| below). | ||
| '#size-cells': | ||
| const: 0 | ||
|
|
||
| patternProperties: | ||
| '^cpu@[0-9a-f]+$': | ||
| properties: | ||
| compatible: | ||
| type: array | ||
| items: | ||
| - enum: | ||
| - sifive,rocket0 | ||
| - sifive,e5 | ||
| - sifive,e51 | ||
| - sifive,u54-mc | ||
| - sifive,u54 | ||
| - sifive,u5 | ||
| - const: riscv | ||
| description: | ||
| Identifies that the hart uses the RISC-V instruction set | ||
| and identifies the type of the hart. | ||
|
|
||
| mmu-type: | ||
| allOf: | ||
| - $ref: "/schemas/types.yaml#/definitions/string" | ||
| - enum: | ||
| - riscv,sv32 | ||
| - riscv,sv39 | ||
| - riscv,sv48 | ||
| description: | ||
| Identifies the MMU address translation mode used on this | ||
| hart. These values originate from the RISC-V Privileged | ||
| Specification document, available from | ||
| https://riscv.org/specifications/ | ||
|
|
||
| riscv,isa: | ||
| allOf: | ||
| - $ref: "/schemas/types.yaml#/definitions/string" | ||
| - enum: | ||
| - rv64imac | ||
| - rv64imafdc | ||
| description: | ||
| Identifies the specific RISC-V instruction set architecture | ||
| supported by the hart. These are documented in the RISC-V | ||
| User-Level ISA document, available from | ||
| https://riscv.org/specifications/ | ||
|
|
||
| timebase-frequency: | ||
| type: integer | ||
| minimum: 1 | ||
| description: | ||
| Specifies the clock frequency of the system timer in Hz. | ||
| This value is common to all harts on a single system image. | ||
|
|
||
| interrupt-controller: | ||
| type: object | ||
| description: Describes the CPU's local interrupt controller | ||
|
|
||
| properties: | ||
| '#interrupt-cells': | ||
| const: 1 | ||
|
|
||
| compatible: | ||
| const: riscv,cpu-intc | ||
|
|
||
| interrupt-controller: true | ||
|
|
||
| required: | ||
| - '#interrupt-cells' | ||
| - compatible | ||
| - interrupt-controller | ||
|
|
||
| required: | ||
| - riscv,isa | ||
| - timebase-frequency | ||
| - interrupt-controller | ||
|
|
||
| examples: | ||
| - | | ||
| // Example 1: SiFive Freedom U540G Development Kit | ||
| cpus { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| timebase-frequency = <1000000>; | ||
| cpu@0 { | ||
| clock-frequency = <0>; | ||
| compatible = "sifive,rocket0", "riscv"; | ||
| device_type = "cpu"; | ||
| i-cache-block-size = <64>; | ||
| i-cache-sets = <128>; | ||
| i-cache-size = <16384>; | ||
| reg = <0>; | ||
| riscv,isa = "rv64imac"; | ||
| cpu_intc0: interrupt-controller { | ||
| #interrupt-cells = <1>; | ||
| compatible = "riscv,cpu-intc"; | ||
| interrupt-controller; | ||
| }; | ||
| }; | ||
| cpu@1 { | ||
| clock-frequency = <0>; | ||
| compatible = "sifive,rocket0", "riscv"; | ||
| d-cache-block-size = <64>; | ||
| d-cache-sets = <64>; | ||
| d-cache-size = <32768>; | ||
| d-tlb-sets = <1>; | ||
| d-tlb-size = <32>; | ||
| device_type = "cpu"; | ||
| i-cache-block-size = <64>; | ||
| i-cache-sets = <64>; | ||
| i-cache-size = <32768>; | ||
| i-tlb-sets = <1>; | ||
| i-tlb-size = <32>; | ||
| mmu-type = "riscv,sv39"; | ||
| reg = <1>; | ||
| riscv,isa = "rv64imafdc"; | ||
| tlb-split; | ||
| cpu_intc1: interrupt-controller { | ||
| #interrupt-cells = <1>; | ||
| compatible = "riscv,cpu-intc"; | ||
| interrupt-controller; | ||
| }; | ||
| }; | ||
| }; | ||
| - | | ||
| // Example 2: Spike ISA Simulator with 1 Hart | ||
| cpus { | ||
| cpu@0 { | ||
| device_type = "cpu"; | ||
| reg = <0>; | ||
| compatible = "riscv"; | ||
| riscv,isa = "rv64imafdc"; | ||
| mmu-type = "riscv,sv48"; | ||
| interrupt-controller { | ||
| #interrupt-cells = <1>; | ||
| interrupt-controller; | ||
| compatible = "riscv,cpu-intc"; | ||
| }; | ||
| }; | ||
| }; | ||
| ... |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,25 @@ | ||
| # SPDX-License-Identifier: (GPL-2.0 OR MIT) | ||
| %YAML 1.2 | ||
| --- | ||
| $id: http://devicetree.org/schemas/riscv/sifive.yaml# | ||
| $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
|
|
||
| title: SiFive SoC-based boards | ||
|
|
||
| maintainers: | ||
| - Paul Walmsley <paul.walmsley@sifive.com> | ||
| - Palmer Dabbelt <palmer@sifive.com> | ||
|
|
||
| description: | ||
| SiFive SoC-based boards | ||
|
|
||
| properties: | ||
| $nodename: | ||
| const: '/' | ||
| compatible: | ||
| items: | ||
| - enum: | ||
| - sifive,freedom-unleashed-a00 | ||
| - const: sifive,fu540-c000 | ||
| - const: sifive,fu540 | ||
| ... |
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