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arm64: dts: ti: Add support for J7200 SoC
The J7200 SoC is a part of the K3 Multicore SoC architecture platform. It is targeted for automotive gateway, vehicle compute systems, Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications. The SoC aims to meet the complex processing needs of modern embedded products. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, two clusters of lockstep capable dual Cortex-R5F MCUs and a Centralized Device Management and Security Controller (DMSC). * Configurable L3 Cache and IO-coherent architecture with high data throughput capable distributed DMA architecture under NAVSS. * Integrated Ethernet switch supporting up to a total of 4 external ports in addition to legacy Ethernet switch of up to 2 ports. * Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems, 20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and I2C, eCAP/eQEP, eHRPWM among other peripherals. * One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL management. See J7200 Technical Reference Manual (SPRUIU1, June 2020) for further details: https://www.ti.com/lit/pdf/spruiu1 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20200914162231.2535-5-lokeshvutla@ti.com
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Lokesh Vutla
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Nishanth Menon
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Sep 23, 2020
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| // SPDX-License-Identifier: GPL-2.0 | ||
| /* | ||
| * Device Tree Source for J7200 SoC Family Main Domain peripherals | ||
| * | ||
| * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ | ||
| */ | ||
|
|
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| &cbass_main { | ||
| msmc_ram: sram@70000000 { | ||
| compatible = "mmio-sram"; | ||
| reg = <0x00 0x70000000 0x00 0x100000>; | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
| ranges = <0x00 0x00 0x70000000 0x100000>; | ||
|
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| atf-sram@0 { | ||
| reg = <0x00 0x20000>; | ||
| }; | ||
| }; | ||
|
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| gic500: interrupt-controller@1800000 { | ||
| compatible = "arm,gic-v3"; | ||
| #address-cells = <2>; | ||
| #size-cells = <2>; | ||
| ranges; | ||
| #interrupt-cells = <3>; | ||
| interrupt-controller; | ||
| reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ | ||
| <0x00 0x01900000 0x00 0x100000>; /* GICR */ | ||
|
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| /* vcpumntirq: virtual CPU interface maintenance interrupt */ | ||
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; | ||
|
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| gic_its: msi-controller@1820000 { | ||
| compatible = "arm,gic-v3-its"; | ||
| reg = <0x00 0x01820000 0x00 0x10000>; | ||
| socionext,synquacer-pre-its = <0x1000000 0x400000>; | ||
| msi-controller; | ||
| #msi-cells = <1>; | ||
| }; | ||
| }; | ||
|
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| main_gpio_intr: interrupt-controller0 { | ||
| compatible = "ti,sci-intr"; | ||
| ti,intr-trigger-type = <1>; | ||
| interrupt-controller; | ||
| interrupt-parent = <&gic500>; | ||
| #interrupt-cells = <1>; | ||
| ti,sci = <&dmsc>; | ||
| ti,sci-dev-id = <131>; | ||
| ti,interrupt-ranges = <8 392 56>; | ||
| }; | ||
|
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||
| main_navss: bus@30000000 { | ||
| compatible = "simple-mfd"; | ||
| #address-cells = <2>; | ||
| #size-cells = <2>; | ||
| ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; | ||
| ti,sci-dev-id = <199>; | ||
|
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| main_navss_intr: interrupt-controller1 { | ||
| compatible = "ti,sci-intr"; | ||
| ti,intr-trigger-type = <4>; | ||
| interrupt-controller; | ||
| interrupt-parent = <&gic500>; | ||
| #interrupt-cells = <1>; | ||
| ti,sci = <&dmsc>; | ||
| ti,sci-dev-id = <213>; | ||
| ti,interrupt-ranges = <0 64 64>, | ||
| <64 448 64>, | ||
| <128 672 64>; | ||
| }; | ||
|
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||
| main_udmass_inta: msi-controller@33d00000 { | ||
| compatible = "ti,sci-inta"; | ||
| reg = <0x00 0x33d00000 0x00 0x100000>; | ||
| interrupt-controller; | ||
| #interrupt-cells = <0>; | ||
| interrupt-parent = <&main_navss_intr>; | ||
| msi-controller; | ||
| ti,sci = <&dmsc>; | ||
| ti,sci-dev-id = <209>; | ||
| ti,interrupt-ranges = <0 0 256>; | ||
| }; | ||
|
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||
| secure_proxy_main: mailbox@32c00000 { | ||
| compatible = "ti,am654-secure-proxy"; | ||
| #mbox-cells = <1>; | ||
| reg-names = "target_data", "rt", "scfg"; | ||
| reg = <0x00 0x32c00000 0x00 0x100000>, | ||
| <0x00 0x32400000 0x00 0x100000>, | ||
| <0x00 0x32800000 0x00 0x100000>; | ||
| interrupt-names = "rx_011"; | ||
| interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | ||
| }; | ||
| }; | ||
|
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||
| main_pmx0: pinctrl@11c000 { | ||
| compatible = "pinctrl-single"; | ||
| /* Proxy 0 addressing */ | ||
| reg = <0x00 0x11c000 0x00 0x2b4>; | ||
| #pinctrl-cells = <1>; | ||
| pinctrl-single,register-width = <32>; | ||
| pinctrl-single,function-mask = <0xffffffff>; | ||
| }; | ||
|
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||
| main_uart0: serial@2800000 { | ||
| compatible = "ti,j721e-uart", "ti,am654-uart"; | ||
| reg = <0x00 0x02800000 0x00 0x100>; | ||
| reg-shift = <2>; | ||
| reg-io-width = <4>; | ||
| interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; | ||
| clock-frequency = <48000000>; | ||
| current-speed = <115200>; | ||
| power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; | ||
| clocks = <&k3_clks 146 2>; | ||
| clock-names = "fclk"; | ||
| }; | ||
|
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||
| main_uart1: serial@2810000 { | ||
| compatible = "ti,j721e-uart", "ti,am654-uart"; | ||
| reg = <0x00 0x02810000 0x00 0x100>; | ||
| reg-shift = <2>; | ||
| reg-io-width = <4>; | ||
| interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; | ||
| clock-frequency = <48000000>; | ||
| current-speed = <115200>; | ||
| power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; | ||
| clocks = <&k3_clks 278 2>; | ||
| clock-names = "fclk"; | ||
| }; | ||
|
|
||
| main_uart2: serial@2820000 { | ||
| compatible = "ti,j721e-uart", "ti,am654-uart"; | ||
| reg = <0x00 0x02820000 0x00 0x100>; | ||
| reg-shift = <2>; | ||
| reg-io-width = <4>; | ||
| interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; | ||
| clock-frequency = <48000000>; | ||
| current-speed = <115200>; | ||
| power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; | ||
| clocks = <&k3_clks 279 2>; | ||
| clock-names = "fclk"; | ||
| }; | ||
|
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||
| main_uart3: serial@2830000 { | ||
| compatible = "ti,j721e-uart", "ti,am654-uart"; | ||
| reg = <0x00 0x02830000 0x00 0x100>; | ||
| reg-shift = <2>; | ||
| reg-io-width = <4>; | ||
| interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; | ||
| clock-frequency = <48000000>; | ||
| current-speed = <115200>; | ||
| power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; | ||
| clocks = <&k3_clks 280 2>; | ||
| clock-names = "fclk"; | ||
| }; | ||
|
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||
| main_uart4: serial@2840000 { | ||
| compatible = "ti,j721e-uart", "ti,am654-uart"; | ||
| reg = <0x00 0x02840000 0x00 0x100>; | ||
| reg-shift = <2>; | ||
| reg-io-width = <4>; | ||
| interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; | ||
| clock-frequency = <48000000>; | ||
| current-speed = <115200>; | ||
| power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; | ||
| clocks = <&k3_clks 281 2>; | ||
| clock-names = "fclk"; | ||
| }; | ||
|
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||
| main_uart5: serial@2850000 { | ||
| compatible = "ti,j721e-uart", "ti,am654-uart"; | ||
| reg = <0x00 0x02850000 0x00 0x100>; | ||
| reg-shift = <2>; | ||
| reg-io-width = <4>; | ||
| interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; | ||
| clock-frequency = <48000000>; | ||
| current-speed = <115200>; | ||
| power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; | ||
| clocks = <&k3_clks 282 2>; | ||
| clock-names = "fclk"; | ||
| }; | ||
|
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||
| main_uart6: serial@2860000 { | ||
| compatible = "ti,j721e-uart", "ti,am654-uart"; | ||
| reg = <0x00 0x02860000 0x00 0x100>; | ||
| reg-shift = <2>; | ||
| reg-io-width = <4>; | ||
| interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; | ||
| clock-frequency = <48000000>; | ||
| current-speed = <115200>; | ||
| power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; | ||
| clocks = <&k3_clks 283 2>; | ||
| clock-names = "fclk"; | ||
| }; | ||
|
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||
| main_uart7: serial@2870000 { | ||
| compatible = "ti,j721e-uart", "ti,am654-uart"; | ||
| reg = <0x00 0x02870000 0x00 0x100>; | ||
| reg-shift = <2>; | ||
| reg-io-width = <4>; | ||
| interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; | ||
| clock-frequency = <48000000>; | ||
| current-speed = <115200>; | ||
| power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; | ||
| clocks = <&k3_clks 284 2>; | ||
| clock-names = "fclk"; | ||
| }; | ||
|
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||
| main_uart8: serial@2880000 { | ||
| compatible = "ti,j721e-uart", "ti,am654-uart"; | ||
| reg = <0x00 0x02880000 0x00 0x100>; | ||
| reg-shift = <2>; | ||
| reg-io-width = <4>; | ||
| interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; | ||
| clock-frequency = <48000000>; | ||
| current-speed = <115200>; | ||
| power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; | ||
| clocks = <&k3_clks 285 2>; | ||
| clock-names = "fclk"; | ||
| }; | ||
|
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||
| main_uart9: serial@2890000 { | ||
| compatible = "ti,j721e-uart", "ti,am654-uart"; | ||
| reg = <0x00 0x02890000 0x00 0x100>; | ||
| reg-shift = <2>; | ||
| reg-io-width = <4>; | ||
| interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; | ||
| clock-frequency = <48000000>; | ||
| current-speed = <115200>; | ||
| power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; | ||
| clocks = <&k3_clks 286 2>; | ||
| clock-names = "fclk"; | ||
| }; | ||
| }; |
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| // SPDX-License-Identifier: GPL-2.0 | ||
| /* | ||
| * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals | ||
| * | ||
| * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ | ||
| */ | ||
|
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||
| &cbass_mcu_wakeup { | ||
| dmsc: dmsc@44083000 { | ||
| compatible = "ti,k2g-sci"; | ||
| ti,host-id = <12>; | ||
|
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| mbox-names = "rx", "tx"; | ||
|
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| mboxes= <&secure_proxy_main 11>, | ||
| <&secure_proxy_main 13>; | ||
|
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| reg-names = "debug_messages"; | ||
| reg = <0x00 0x44083000 0x00 0x1000>; | ||
|
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| k3_pds: power-controller { | ||
| compatible = "ti,sci-pm-domain"; | ||
| #power-domain-cells = <2>; | ||
| }; | ||
|
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| k3_clks: clocks { | ||
| compatible = "ti,k2g-sci-clk"; | ||
| #clock-cells = <2>; | ||
| }; | ||
|
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| k3_reset: reset-controller { | ||
| compatible = "ti,sci-reset"; | ||
| #reset-cells = <2>; | ||
| }; | ||
| }; | ||
|
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| chipid@43000014 { | ||
| compatible = "ti,am654-chipid"; | ||
| reg = <0x00 0x43000014 0x00 0x4>; | ||
| }; | ||
|
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||
| wkup_pmx0: pinctrl@4301c000 { | ||
| compatible = "pinctrl-single"; | ||
| /* Proxy 0 addressing */ | ||
| reg = <0x00 0x4301c000 0x00 0x178>; | ||
| #pinctrl-cells = <1>; | ||
| pinctrl-single,register-width = <32>; | ||
| pinctrl-single,function-mask = <0xffffffff>; | ||
| }; | ||
|
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||
| mcu_ram: sram@41c00000 { | ||
| compatible = "mmio-sram"; | ||
| reg = <0x00 0x41c00000 0x00 0x100000>; | ||
| ranges = <0x00 0x00 0x41c00000 0x100000>; | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
| }; | ||
|
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| wkup_uart0: serial@42300000 { | ||
| compatible = "ti,j721e-uart", "ti,am654-uart"; | ||
| reg = <0x00 0x42300000 0x00 0x100>; | ||
| reg-shift = <2>; | ||
| reg-io-width = <4>; | ||
| interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; | ||
| clock-frequency = <48000000>; | ||
| current-speed = <115200>; | ||
| power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; | ||
| clocks = <&k3_clks 287 2>; | ||
| clock-names = "fclk"; | ||
| }; | ||
|
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| mcu_uart0: serial@40a00000 { | ||
| compatible = "ti,j721e-uart", "ti,am654-uart"; | ||
| reg = <0x00 0x40a00000 0x00 0x100>; | ||
| reg-shift = <2>; | ||
| reg-io-width = <4>; | ||
| interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; | ||
| clock-frequency = <96000000>; | ||
| current-speed = <115200>; | ||
| power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; | ||
| clocks = <&k3_clks 149 2>; | ||
| clock-names = "fclk"; | ||
| }; | ||
|
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| wkup_gpio_intr: interrupt-controller2 { | ||
| compatible = "ti,sci-intr"; | ||
| ti,intr-trigger-type = <1>; | ||
| interrupt-controller; | ||
| interrupt-parent = <&gic500>; | ||
| #interrupt-cells = <1>; | ||
| ti,sci = <&dmsc>; | ||
| ti,sci-dev-id = <137>; | ||
| ti,interrupt-ranges = <16 960 16>; | ||
| }; | ||
| }; |
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