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arm64: dts: uniphier: Add USB3 controller nodes
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Add USB3 controller nodes including usb-core, resets, regulator, ss-phy
and hs-phy. This supports for LD20, PXs3 and the boards. This includes
additional efuse nodes for obtaining PHY trimming values.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Kunihiko Hayashi authored and Masahiro Yamada committed Oct 4, 2018
1 parent 8bb2f53 commit d7b9beb
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4 changes: 4 additions & 0 deletions arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts
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Expand Up @@ -148,3 +148,7 @@
&nand {
status = "okay";
};

&usb {
status = "okay";
};
4 changes: 4 additions & 0 deletions arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
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Expand Up @@ -75,3 +75,7 @@
drive-strength = <9>;
};
};

&usb {
status = "okay";
};
194 changes: 194 additions & 0 deletions arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
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Expand Up @@ -611,6 +611,50 @@
efuse@200 {
compatible = "socionext,uniphier-efuse";
reg = <0x200 0x68>;
#address-cells = <1>;
#size-cells = <1>;

/* USB cells */
usb_rterm0: trim@54,4 {
reg = <0x54 1>;
bits = <4 2>;
};
usb_rterm1: trim@55,4 {
reg = <0x55 1>;
bits = <4 2>;
};
usb_rterm2: trim@58,4 {
reg = <0x58 1>;
bits = <4 2>;
};
usb_rterm3: trim@59,4 {
reg = <0x59 1>;
bits = <4 2>;
};
usb_sel_t0: trim@54,0 {
reg = <0x54 1>;
bits = <0 4>;
};
usb_sel_t1: trim@55,0 {
reg = <0x55 1>;
bits = <0 4>;
};
usb_sel_t2: trim@58,0 {
reg = <0x58 1>;
bits = <0 4>;
};
usb_sel_t3: trim@59,0 {
reg = <0x59 1>;
bits = <0 4>;
};
usb_hs_i0: trim@56,0 {
reg = <0x56 1>;
bits = <0 4>;
};
usb_hs_i2: trim@5a,0 {
reg = <0x5a 1>;
bits = <0 4>;
};
};
};

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};
};

usb: usb@65a00000 {
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
status = "disabled";
reg = <0x65a00000 0xcd00>;
interrupt-names = "host";
interrupts = <0 134 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
<&pinctrl_usb2>, <&pinctrl_usb3>;
clock-names = "ref", "bus_early", "suspend";
clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
resets = <&usb_rst 15>;
phys = <&usb_hsphy0>, <&usb_hsphy1>,
<&usb_hsphy2>, <&usb_hsphy3>,
<&usb_ssphy0>, <&usb_ssphy1>;
dr_mode = "host";
};

usb-glue@65b00000 {
compatible = "socionext,uniphier-ld20-dwc3-glue",
"simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65b00000 0x400>;

usb_rst: reset@0 {
compatible = "socionext,uniphier-ld20-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
clock-names = "link";
clocks = <&sys_clk 14>;
reset-names = "link";
resets = <&sys_rst 14>;
};

usb_vbus0: regulator@100 {
compatible = "socionext,uniphier-ld20-usb3-regulator";
reg = <0x100 0x10>;
clock-names = "link";
clocks = <&sys_clk 14>;
reset-names = "link";
resets = <&sys_rst 14>;
};

usb_vbus1: regulator@110 {
compatible = "socionext,uniphier-ld20-usb3-regulator";
reg = <0x110 0x10>;
clock-names = "link";
clocks = <&sys_clk 14>;
reset-names = "link";
resets = <&sys_rst 14>;
};

usb_vbus2: regulator@120 {
compatible = "socionext,uniphier-ld20-usb3-regulator";
reg = <0x120 0x10>;
clock-names = "link";
clocks = <&sys_clk 14>;
reset-names = "link";
resets = <&sys_rst 14>;
};

usb_vbus3: regulator@130 {
compatible = "socionext,uniphier-ld20-usb3-regulator";
reg = <0x130 0x10>;
clock-names = "link";
clocks = <&sys_clk 14>;
reset-names = "link";
resets = <&sys_rst 14>;
};

usb_hsphy0: hs-phy@200 {
compatible = "socionext,uniphier-ld20-usb3-hsphy";
reg = <0x200 0x10>;
#phy-cells = <0>;
clock-names = "link", "phy";
clocks = <&sys_clk 14>, <&sys_clk 16>;
reset-names = "link", "phy";
resets = <&sys_rst 14>, <&sys_rst 16>;
vbus-supply = <&usb_vbus0>;
nvmem-cell-names = "rterm", "sel_t", "hs_i";
nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
<&usb_hs_i0>;
};

usb_hsphy1: hs-phy@210 {
compatible = "socionext,uniphier-ld20-usb3-hsphy";
reg = <0x210 0x10>;
#phy-cells = <0>;
clock-names = "link", "phy";
clocks = <&sys_clk 14>, <&sys_clk 16>;
reset-names = "link", "phy";
resets = <&sys_rst 14>, <&sys_rst 16>;
vbus-supply = <&usb_vbus1>;
nvmem-cell-names = "rterm", "sel_t", "hs_i";
nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
<&usb_hs_i0>;
};

usb_hsphy2: hs-phy@220 {
compatible = "socionext,uniphier-ld20-usb3-hsphy";
reg = <0x220 0x10>;
#phy-cells = <0>;
clock-names = "link", "phy";
clocks = <&sys_clk 14>, <&sys_clk 17>;
reset-names = "link", "phy";
resets = <&sys_rst 14>, <&sys_rst 17>;
vbus-supply = <&usb_vbus2>;
nvmem-cell-names = "rterm", "sel_t", "hs_i";
nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
<&usb_hs_i2>;
};

usb_hsphy3: hs-phy@230 {
compatible = "socionext,uniphier-ld20-usb3-hsphy";
reg = <0x230 0x10>;
#phy-cells = <0>;
clock-names = "link", "phy";
clocks = <&sys_clk 14>, <&sys_clk 17>;
reset-names = "link", "phy";
resets = <&sys_rst 14>, <&sys_rst 17>;
vbus-supply = <&usb_vbus3>;
nvmem-cell-names = "rterm", "sel_t", "hs_i";
nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
<&usb_hs_i2>;
};

usb_ssphy0: ss-phy@300 {
compatible = "socionext,uniphier-ld20-usb3-ssphy";
reg = <0x300 0x10>;
#phy-cells = <0>;
clock-names = "link", "phy";
clocks = <&sys_clk 14>, <&sys_clk 18>;
reset-names = "link", "phy";
resets = <&sys_rst 14>, <&sys_rst 18>;
vbus-supply = <&usb_vbus0>;
};

usb_ssphy1: ss-phy@310 {
compatible = "socionext,uniphier-ld20-usb3-ssphy";
reg = <0x310 0x10>;
#phy-cells = <0>;
clock-names = "link", "phy";
clocks = <&sys_clk 14>, <&sys_clk 19>;
reset-names = "link", "phy";
resets = <&sys_rst 14>, <&sys_rst 19>;
vbus-supply = <&usb_vbus1>;
};
};

nand: nand@68000000 {
compatible = "socionext,uniphier-denali-nand-v5b";
status = "disabled";
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8 changes: 8 additions & 0 deletions arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
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Expand Up @@ -104,3 +104,11 @@
&nand {
status = "okay";
};

&usb0 {
status = "okay";
};

&usb1 {
status = "okay";
};
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