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Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel…
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…/git/mellanox/linux

Tariq Toukan says:

====================
mlx5-next updates 2025-01-14

The following pull-request contains mlx5 IFC updates.

* 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux:
  net/mlx5: Add nic_cap_reg and vhca_icm_ctrl registers
  net/mlx5: SHAMPO: Introduce new SHAMPO specific HCA caps
  net/mlx5: Add support for MRTCQ register
  net/mlx5: Update mlx5_ifc to support FEC for 200G per lane link modes
====================

Link: https://patch.msgid.link/20250114055700.1928736-1-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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Jakub Kicinski committed Jan 14, 2025
2 parents 9c7ad35 + 6ca00ec commit d90e36f
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Showing 5 changed files with 86 additions and 5 deletions.
6 changes: 6 additions & 0 deletions drivers/net/ethernet/mellanox/mlx5/core/fw.c
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Original file line number Diff line number Diff line change
Expand Up @@ -281,6 +281,12 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
return err;
}

if (MLX5_CAP_GEN(dev, shampo)) {
err = mlx5_core_get_caps_mode(dev, MLX5_CAP_SHAMPO, HCA_CAP_OPMOD_GET_CUR);
if (err)
return err;
}

return 0;
}

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5 changes: 5 additions & 0 deletions drivers/net/ethernet/mellanox/mlx5/core/main.c
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Original file line number Diff line number Diff line change
Expand Up @@ -368,6 +368,10 @@ int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_ty
u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
int err;

if (WARN_ON(!dev->caps.hca[cap_type]))
/* this cap_type must be added to mlx5_hca_caps_alloc() */
return -EINVAL;

memset(in, 0, sizeof(in));
out = kzalloc(out_sz, GFP_KERNEL);
if (!out)
Expand Down Expand Up @@ -1790,6 +1794,7 @@ static const int types[] = {
MLX5_CAP_MACSEC,
MLX5_CAP_ADV_VIRTUALIZATION,
MLX5_CAP_CRYPTO,
MLX5_CAP_SHAMPO,
};

static void mlx5_hca_caps_free(struct mlx5_core_dev *dev)
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4 changes: 4 additions & 0 deletions include/linux/mlx5/device.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1245,6 +1245,7 @@ enum mlx5_cap_type {
MLX5_CAP_DEV_EVENT = 0x14,
MLX5_CAP_IPSEC,
MLX5_CAP_CRYPTO = 0x1a,
MLX5_CAP_SHAMPO = 0x1d,
MLX5_CAP_MACSEC = 0x1f,
MLX5_CAP_GENERAL_2 = 0x20,
MLX5_CAP_PORT_SELECTION = 0x25,
Expand Down Expand Up @@ -1470,6 +1471,9 @@ enum mlx5_qcam_feature_groups {
#define MLX5_CAP_MACSEC(mdev, cap)\
MLX5_GET(macsec_cap, (mdev)->caps.hca[MLX5_CAP_MACSEC]->cur, cap)

#define MLX5_CAP_SHAMPO(mdev, cap) \
MLX5_GET(shampo_cap, mdev->caps.hca[MLX5_CAP_SHAMPO]->cur, cap)

enum {
MLX5_CMD_STAT_OK = 0x0,
MLX5_CMD_STAT_INT_ERR = 0x1,
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3 changes: 3 additions & 0 deletions include/linux/mlx5/driver.h
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Original file line number Diff line number Diff line change
Expand Up @@ -160,9 +160,12 @@ enum {
MLX5_REG_MIRC = 0x9162,
MLX5_REG_MTPTM = 0x9180,
MLX5_REG_MTCTR = 0x9181,
MLX5_REG_MRTCQ = 0x9182,
MLX5_REG_SBCAM = 0xB01F,
MLX5_REG_RESOURCE_DUMP = 0xC000,
MLX5_REG_NIC_CAP = 0xC00D,
MLX5_REG_DTOR = 0xC00E,
MLX5_REG_VHCA_ICM_CTRL = 0xC010,
};

enum mlx5_qpts_trust_state {
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73 changes: 68 additions & 5 deletions include/linux/mlx5/mlx5_ifc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1830,7 +1830,7 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 regexp_params[0x1];
u8 uar_sz[0x6];
u8 port_selection_cap[0x1];
u8 reserved_at_251[0x1];
u8 nic_cap_reg[0x1];
u8 umem_uid_0[0x1];
u8 reserved_at_253[0x5];
u8 log_pg_sz[0x8];
Expand Down Expand Up @@ -2329,7 +2329,9 @@ struct mlx5_ifc_wq_bits {
u8 headers_mkey[0x20];

u8 shampo_enable[0x1];
u8 reserved_at_1e1[0x4];
u8 reserved_at_1e1[0x1];
u8 shampo_mode[0x2];
u8 reserved_at_1e4[0x1];
u8 log_reservation_size[0x3];
u8 reserved_at_1e8[0x5];
u8 log_max_num_of_packets_per_reservation[0x3];
Expand Down Expand Up @@ -3327,6 +3329,14 @@ struct mlx5_ifc_dropped_packet_logged_bits {
u8 reserved_at_0[0xe0];
};

struct mlx5_ifc_nic_cap_reg_bits {
u8 reserved_at_0[0x1a];
u8 vhca_icm_ctrl[0x1];
u8 reserved_at_1b[0x5];

u8 reserved_at_20[0x60];
};

struct mlx5_ifc_default_timeout_bits {
u8 to_multiplier[0x3];
u8 reserved_at_3[0x9];
Expand Down Expand Up @@ -3363,6 +3373,18 @@ struct mlx5_ifc_dtor_reg_bits {
u8 reserved_at_1c0[0x20];
};

struct mlx5_ifc_vhca_icm_ctrl_reg_bits {
u8 vhca_id_valid[0x1];
u8 reserved_at_1[0xf];
u8 vhca_id[0x10];

u8 reserved_at_20[0xa0];

u8 cur_alloc_icm[0x20];

u8 reserved_at_e0[0x120];
};

enum {
MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
Expand Down Expand Up @@ -3701,6 +3723,22 @@ struct mlx5_ifc_crypto_cap_bits {
u8 reserved_at_80[0x780];
};

struct mlx5_ifc_shampo_cap_bits {
u8 reserved_at_0[0x3];
u8 shampo_log_max_reservation_size[0x5];
u8 reserved_at_8[0x3];
u8 shampo_log_min_reservation_size[0x5];
u8 shampo_min_mss_size[0x10];

u8 shampo_header_split[0x1];
u8 shampo_header_split_data_merge[0x1];
u8 reserved_at_22[0x1];
u8 shampo_log_max_headers_entry_size[0x5];
u8 reserved_at_28[0x18];

u8 reserved_at_40[0x7c0];
};

union mlx5_ifc_hca_cap_union_bits {
struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
Expand Down Expand Up @@ -10153,7 +10191,21 @@ struct mlx5_ifc_pplm_reg_bits {
u8 fec_override_admin_200g_2x[0x10];
u8 fec_override_admin_100g_1x[0x10];

u8 reserved_at_260[0x20];
u8 reserved_at_260[0x60];

u8 fec_override_cap_1600g_8x[0x10];
u8 fec_override_cap_800g_4x[0x10];

u8 fec_override_cap_400g_2x[0x10];
u8 fec_override_cap_200g_1x[0x10];

u8 fec_override_admin_1600g_8x[0x10];
u8 fec_override_admin_800g_4x[0x10];

u8 fec_override_admin_400g_2x[0x10];
u8 fec_override_admin_200g_1x[0x10];

u8 reserved_at_340[0x80];
};

struct mlx5_ifc_ppcnt_reg_bits {
Expand Down Expand Up @@ -10527,7 +10579,9 @@ struct mlx5_ifc_mtutc_reg_bits {
};

struct mlx5_ifc_pcam_enhanced_features_bits {
u8 reserved_at_0[0x48];
u8 reserved_at_0[0x1d];
u8 fec_200G_per_lane_in_pplm[0x1];
u8 reserved_at_1e[0x2a];
u8 fec_100G_per_lane_in_pplm[0x1];
u8 reserved_at_49[0x1f];
u8 fec_50G_per_lane_in_pplm[0x1];
Expand Down Expand Up @@ -10667,7 +10721,8 @@ struct mlx5_ifc_mcam_access_reg_bits3 {

u8 regs_63_to_32[0x20];

u8 regs_31_to_2[0x1e];
u8 regs_31_to_3[0x1d];
u8 mrtcq[0x1];
u8 mtctr[0x1];
u8 mtptm[0x1];
};
Expand Down Expand Up @@ -13158,4 +13213,12 @@ struct mlx5_ifc_msees_reg_bits {
u8 reserved_at_80[0x180];
};

struct mlx5_ifc_mrtcq_reg_bits {
u8 reserved_at_0[0x40];

u8 rt_clock_identity[0x40];

u8 reserved_at_80[0x180];
};

#endif /* MLX5_IFC_H */

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