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dt-bindings: PCI: uniphier: Convert uniphier-pcie.txt to json-schema
Convert the file into a JSON description at the yaml format. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1648617814-9217-2-git-send-email-hayashi.kunihiko@socionext.com
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Kunihiko Hayashi
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Rob Herring
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Apr 5, 2022
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Documentation/devicetree/bindings/pci/socionext,uniphier-pcie.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: Socionext UniPhier PCIe host controller | ||
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description: | | ||
UniPhier PCIe host controller is based on the Synopsys DesignWare | ||
PCI core. It shares common features with the PCIe DesignWare core and | ||
inherits common properties defined in | ||
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml. | ||
maintainers: | ||
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com> | ||
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allOf: | ||
- $ref: /schemas/pci/snps,dw-pcie.yaml# | ||
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properties: | ||
compatible: | ||
enum: | ||
- socionext,uniphier-pcie | ||
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reg: | ||
minItems: 3 | ||
maxItems: 4 | ||
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reg-names: | ||
minItems: 3 | ||
items: | ||
- const: dbi | ||
- const: link | ||
- const: config | ||
- const: atu | ||
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clocks: | ||
maxItems: 1 | ||
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resets: | ||
maxItems: 1 | ||
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num-viewport: true | ||
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num-lanes: true | ||
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phys: | ||
maxItems: 1 | ||
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phy-names: | ||
const: pcie-phy | ||
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required: | ||
- compatible | ||
- reg | ||
- reg-names | ||
- clocks | ||
- resets | ||
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unevaluatedProperties: false | ||
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examples: | ||
- | | ||
pcie: pcie@66000000 { | ||
compatible = "socionext,uniphier-pcie"; | ||
reg-names = "dbi", "link", "config"; | ||
reg = <0x66000000 0x1000>, <0x66010000 0x10000>, <0x2fff0000 0x10000>; | ||
#address-cells = <3>; | ||
#size-cells = <2>; | ||
clocks = <&sys_clk 24>; | ||
resets = <&sys_rst 24>; | ||
num-lanes = <1>; | ||
num-viewport = <1>; | ||
bus-range = <0x0 0xff>; | ||
device_type = "pci"; | ||
ranges = <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>, | ||
<0x82000000 0 0x00000000 0x20000000 0 0x0ffe0000>; | ||
phy-names = "pcie-phy"; | ||
phys = <&pcie_phy>; | ||
#interrupt-cells = <1>; | ||
interrupt-names = "dma", "msi"; | ||
interrupts = <0 224 4>, <0 225 4>; | ||
interrupt-map-mask = <0 0 0 7>; | ||
interrupt-map = <0 0 0 1 &pcie_intc 0>, | ||
<0 0 0 2 &pcie_intc 1>, | ||
<0 0 0 3 &pcie_intc 2>, | ||
<0 0 0 4 &pcie_intc 3>; | ||
pcie_intc: legacy-interrupt-controller { | ||
interrupt-controller; | ||
#interrupt-cells = <1>; | ||
interrupt-parent = <&gic>; | ||
interrupts = <0 226 4>; | ||
}; | ||
}; |
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