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clk: qcom: videocc-sm8550: Add SM8650 video clock controller
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Add support to the SM8650 video clock controller by extending
the SM8550 video clock controller, which is mostly identical
but SM8650 has few additional clocks and minor differences.

Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240602114439.1611-5-quic_jkona@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Jagadeesh Kona authored and Bjorn Andersson committed Jun 25, 2024
1 parent 6e18795 commit da1f361
Showing 1 changed file with 149 additions and 4 deletions.
153 changes: 149 additions & 4 deletions drivers/clk/qcom/videocc-sm8550.c
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/

#include <linux/clk-provider.h>
Expand Down Expand Up @@ -35,7 +35,7 @@ static const struct pll_vco lucid_ole_vco[] = {
{ 249600000, 2300000000, 0 },
};

static const struct alpha_pll_config video_cc_pll0_config = {
static struct alpha_pll_config video_cc_pll0_config = {
.l = 0x25,
.alpha = 0x8000,
.config_ctl_val = 0x20485699,
Expand Down Expand Up @@ -66,7 +66,7 @@ static struct clk_alpha_pll video_cc_pll0 = {
},
};

static const struct alpha_pll_config video_cc_pll1_config = {
static struct alpha_pll_config video_cc_pll1_config = {
.l = 0x36,
.alpha = 0xb000,
.config_ctl_val = 0x20485699,
Expand Down Expand Up @@ -117,6 +117,14 @@ static const struct clk_parent_data video_cc_parent_data_1[] = {
{ .hw = &video_cc_pll1.clkr.hw },
};

static const struct parent_map video_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
};

static const struct clk_parent_data video_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
};

static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
Expand All @@ -126,6 +134,16 @@ static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
{ }
};

static const struct freq_tbl ftbl_video_cc_mvs0_clk_src_sm8650[] = {
F(588000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(900000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1140000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1305000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1440000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
{ }
};

static struct clk_rcg2 video_cc_mvs0_clk_src = {
.cmd_rcgr = 0x8000,
.mnd_width = 0,
Expand All @@ -149,6 +167,15 @@ static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
{ }
};

static const struct freq_tbl ftbl_video_cc_mvs1_clk_src_sm8650[] = {
F(840000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
F(1110000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
{ }
};

static struct clk_rcg2 video_cc_mvs1_clk_src = {
.cmd_rcgr = 0x8018,
.mnd_width = 0,
Expand All @@ -164,6 +191,26 @@ static struct clk_rcg2 video_cc_mvs1_clk_src = {
},
};

static const struct freq_tbl ftbl_video_cc_xo_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};

static struct clk_rcg2 video_cc_xo_clk_src = {
.cmd_rcgr = 0x810c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_2,
.freq_tbl = ftbl_video_cc_xo_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_xo_clk_src",
.parent_data = video_cc_parent_data_2,
.num_parents = ARRAY_SIZE(video_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};

static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
.reg = 0x80c4,
.shift = 0,
Expand Down Expand Up @@ -244,6 +291,26 @@ static struct clk_branch video_cc_mvs0_clk = {
},
};

static struct clk_branch video_cc_mvs0_shift_clk = {
.halt_reg = 0x8128,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8128,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x8128,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};

static struct clk_branch video_cc_mvs0c_clk = {
.halt_reg = 0x8064,
.halt_check = BRANCH_HALT,
Expand All @@ -262,6 +329,26 @@ static struct clk_branch video_cc_mvs0c_clk = {
},
};

static struct clk_branch video_cc_mvs0c_shift_clk = {
.halt_reg = 0x812c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x812c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x812c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0c_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};

static struct clk_branch video_cc_mvs1_clk = {
.halt_reg = 0x80e0,
.halt_check = BRANCH_HALT_SKIP,
Expand All @@ -282,6 +369,26 @@ static struct clk_branch video_cc_mvs1_clk = {
},
};

static struct clk_branch video_cc_mvs1_shift_clk = {
.halt_reg = 0x8130,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8130,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x8130,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};

static struct clk_branch video_cc_mvs1c_clk = {
.halt_reg = 0x8090,
.halt_check = BRANCH_HALT,
Expand All @@ -300,6 +407,26 @@ static struct clk_branch video_cc_mvs1c_clk = {
},
};

static struct clk_branch video_cc_mvs1c_shift_clk = {
.halt_reg = 0x8134,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8134,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x8134,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1c_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};

static struct gdsc video_cc_mvs0c_gdsc = {
.gdscr = 0x804c,
.en_rest_wait_val = 0x2,
Expand Down Expand Up @@ -363,6 +490,7 @@ static struct clk_regmap *video_cc_sm8550_clocks[] = {
[VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
[VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
[VIDEO_CC_PLL1] = &video_cc_pll1.clkr,
[VIDEO_CC_XO_CLK_SRC] = NULL,
};

static struct gdsc *video_cc_sm8550_gdscs[] = {
Expand Down Expand Up @@ -403,6 +531,7 @@ static struct qcom_cc_desc video_cc_sm8550_desc = {

static const struct of_device_id video_cc_sm8550_match_table[] = {
{ .compatible = "qcom,sm8550-videocc" },
{ .compatible = "qcom,sm8650-videocc" },
{ }
};
MODULE_DEVICE_TABLE(of, video_cc_sm8550_match_table);
Expand All @@ -411,6 +540,7 @@ static int video_cc_sm8550_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
u32 sleep_clk_offset = 0x8140;

ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
Expand All @@ -426,12 +556,27 @@ static int video_cc_sm8550_probe(struct platform_device *pdev)
return PTR_ERR(regmap);
}

if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8650-videocc")) {
sleep_clk_offset = 0x8150;
video_cc_pll0_config.l = 0x1e;
video_cc_pll0_config.alpha = 0xa000;
video_cc_pll1_config.l = 0x2b;
video_cc_pll1_config.alpha = 0xc000;
video_cc_mvs0_clk_src.freq_tbl = ftbl_video_cc_mvs0_clk_src_sm8650;
video_cc_mvs1_clk_src.freq_tbl = ftbl_video_cc_mvs1_clk_src_sm8650;
video_cc_sm8550_clocks[VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr;
video_cc_sm8550_clocks[VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr;
video_cc_sm8550_clocks[VIDEO_CC_MVS1_SHIFT_CLK] = &video_cc_mvs1_shift_clk.clkr;
video_cc_sm8550_clocks[VIDEO_CC_MVS1C_SHIFT_CLK] = &video_cc_mvs1c_shift_clk.clkr;
video_cc_sm8550_clocks[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr;
}

clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);

/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x80f4); /* VIDEO_CC_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x8140); /* VIDEO_CC_SLEEP_CLK */
qcom_branch_set_clk_en(regmap, sleep_clk_offset); /* VIDEO_CC_SLEEP_CLK */
qcom_branch_set_clk_en(regmap, 0x8124); /* VIDEO_CC_XO_CLK */

ret = qcom_cc_really_probe(pdev, &video_cc_sm8550_desc, regmap);
Expand Down

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