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drm/amd/display: Add some DCN401 reg name to macro definitions
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Update macros to cover DCN 4.0.1.

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Aurabindo Pillai authored and Alex Deucher committed Apr 26, 2024
1 parent 08502ce commit da87132
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Showing 9 changed files with 229 additions and 4 deletions.
64 changes: 64 additions & 0 deletions drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
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Original file line number Diff line number Diff line change
Expand Up @@ -236,6 +236,70 @@
ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)

#define ABM_MASK_SH_LIST_DCN401(mask_sh) \
ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
ABM1_HG_VMAX_SEL, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \
BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \
BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \
BL1_PWM_USER_LEVEL, mask_sh), \
ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
ABM_SF(ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA, \
ABM1_ACE_SLOPE_DATA, mask_sh), \
ABM_SF(ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA, \
ABM1_ACE_OFFSET_DATA, mask_sh), \
ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
ABM1_ACE_OFFSET_SLOPE_INDEX, mask_sh), \
ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
ABM1_ACE_THRES_INDEX, mask_sh), \
ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
ABM1_ACE_IGNORE_MASTER_LOCK_EN, mask_sh), \
ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
ABM1_ACE_READBACK_DB_REG_VALUE_EN, mask_sh), \
ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
ABM1_ACE_DBUF_REG_UPDATE_PENDING, mask_sh), \
ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
ABM1_ACE_LOCK, mask_sh), \
ABM_SF(ABM0_DC_ABM1_ACE_THRES_DATA, \
ABM1_ACE_THRES_DATA_1, mask_sh), \
ABM_SF(ABM0_DC_ABM1_ACE_THRES_DATA, \
ABM1_ACE_THRES_DATA_2, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HG_RESULT_DATA, \
ABM1_HG_RESULT_DATA, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HG_RESULT_INDEX, \
ABM1_HG_RESULT_INDEX, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX, \
ABM1_HG_BIN_33_40_SHIFT_INDEX, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG, \
ABM1_HG_BIN_33_64_SHIFT_FLAG, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX, \
ABM1_HG_BIN_41_48_SHIFT_INDEX, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX, \
ABM1_HG_BIN_49_56_SHIFT_INDEX, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX, \
ABM1_HG_BIN_57_64_SHIFT_INDEX, mask_sh)

#define ABM_REG_FIELD_LIST(type) \
type ABM1_HG_NUM_OF_BINS_SEL; \
type ABM1_HG_VMAX_SEL; \
Expand Down
47 changes: 46 additions & 1 deletion drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
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Original file line number Diff line number Diff line change
Expand Up @@ -178,6 +178,26 @@ struct dcn_hubbub_registers {
uint32_t DCHUBBUB_CLOCK_CNTL;
uint32_t DCHUBBUB_MEM_PWR_MODE_CTRL;
uint32_t DCHUBBUB_ARB_QOS_FORCE;
uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A;
uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A;
uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B;
uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B;
uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A;
uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A;
uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B;
uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B;
uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A;
uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A;
uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B;
uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B;
uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A;
uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B;
uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A;
uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B;
uint32_t DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A;
uint32_t DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B;
uint32_t DCHUBBUB_ARB_FRAC_URG_BW_MALL_A;
uint32_t DCHUBBUB_ARB_FRAC_URG_BW_MALL_B;
};

#define HUBBUB_REG_FIELD_LIST_DCN32(type) \
Expand All @@ -200,7 +220,7 @@ struct dcn_hubbub_registers {
type MALL_PREFETCH_COMPLETE;\
type MALL_IN_USE

#define HUBBUB_REG_FIELD_LIST_DCN35(type) \
#define HUBBUB_REG_FIELD_LIST_DCN35(type) \
type DCHUBBUB_FGCG_REP_DIS;\
type DCHUBBUB_ARB_ALLOW_CSTATE_DEEPSLEEP_LEGACY_MODE

Expand Down Expand Up @@ -305,6 +325,7 @@ struct dcn_hubbub_registers {
type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;\
type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D


#define HUBBUB_HVM_REG_FIELD_LIST(type) \
type DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD;\
type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A;\
Expand Down Expand Up @@ -383,13 +404,36 @@ struct dcn_hubbub_registers {
type DET_MEM_PWR_LS_MODE


#define HUBBUB_REG_FIELD_LIST_DCN4_01(type) \
type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A;\
type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A;\
type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B;\
type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B;\
type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A;\
type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A;\
type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B;\
type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B;\
type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A;\
type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A;\
type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B;\
type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B;\
type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A;\
type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B;\
type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A;\
type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B;\
type DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A;\
type DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B;\
type DCHUBBUB_ARB_FRAC_URG_BW_MALL_A;\
type DCHUBBUB_ARB_FRAC_URG_BW_MALL_B

struct dcn_hubbub_shift {
DCN_HUBBUB_REG_FIELD_LIST(uint8_t);
HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t);
HUBBUB_HVM_REG_FIELD_LIST(uint8_t);
HUBBUB_RET_REG_FIELD_LIST(uint8_t);
HUBBUB_REG_FIELD_LIST_DCN32(uint8_t);
HUBBUB_REG_FIELD_LIST_DCN35(uint8_t);
HUBBUB_REG_FIELD_LIST_DCN4_01(uint8_t);
};

struct dcn_hubbub_mask {
Expand All @@ -399,6 +443,7 @@ struct dcn_hubbub_mask {
HUBBUB_RET_REG_FIELD_LIST(uint32_t);
HUBBUB_REG_FIELD_LIST_DCN32(uint32_t);
HUBBUB_REG_FIELD_LIST_DCN35(uint32_t);
HUBBUB_REG_FIELD_LIST_DCN4_01(uint32_t);
};

struct dc;
Expand Down
7 changes: 7 additions & 0 deletions drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
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Original file line number Diff line number Diff line change
Expand Up @@ -593,13 +593,19 @@ struct dcn10_stream_enc_registers {
type DIG_FE_SOCCLK_G_AFMT_CLOCK_ON;\
type DIG_STREAM_LINK_TARGET

#define SE_REG_FIELD_LIST_DCN4_01_COMMON(type) \
type COMPRESSED_PIXEL_FORMAT;\
type DP_VID_N_INTERVAL;\
type DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE

struct dcn10_stream_encoder_shift {
SE_REG_FIELD_LIST_DCN1_0(uint8_t);
uint8_t HDMI_ACP_SEND;
SE_REG_FIELD_LIST_DCN2_0(uint8_t);
SE_REG_FIELD_LIST_DCN3_0(uint8_t);
SE_REG_FIELD_LIST_DCN3_1_COMMON(uint8_t);
SE_REG_FIELD_LIST_DCN3_5_COMMON(uint8_t);
SE_REG_FIELD_LIST_DCN4_01_COMMON(uint32_t);
};

struct dcn10_stream_encoder_mask {
Expand All @@ -609,6 +615,7 @@ struct dcn10_stream_encoder_mask {
SE_REG_FIELD_LIST_DCN3_0(uint32_t);
SE_REG_FIELD_LIST_DCN3_1_COMMON(uint32_t);
SE_REG_FIELD_LIST_DCN3_5_COMMON(uint32_t);
SE_REG_FIELD_LIST_DCN4_01_COMMON(uint32_t);
};

struct dcn10_stream_encoder {
Expand Down
27 changes: 27 additions & 0 deletions drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
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Original file line number Diff line number Diff line change
Expand Up @@ -329,13 +329,37 @@
type DPSTREAMCLK2_GATE_DISABLE;\
type DPSTREAMCLK3_GATE_DISABLE;\

#define DCCG401_REG_FIELD_LIST(type) \
type OTG0_TMDS_PIXEL_RATE_DIV;\
type DPDTO0_INT;\
type OTG1_TMDS_PIXEL_RATE_DIV;\
type DPDTO1_INT;\
type OTG2_TMDS_PIXEL_RATE_DIV;\
type DPDTO2_INT;\
type OTG3_TMDS_PIXEL_RATE_DIV;\
type DPDTO3_INT;\
type SYMCLK32_ROOT_LE2_GATE_DISABLE;\
type SYMCLK32_ROOT_LE3_GATE_DISABLE;\
type SYMCLK32_LE2_GATE_DISABLE;\
type SYMCLK32_LE3_GATE_DISABLE;\
type SYMCLK32_LE2_SRC_SEL;\
type SYMCLK32_LE3_SRC_SEL;\
type SYMCLK32_LE2_EN;\
type SYMCLK32_LE3_EN;\
type DP_DTO_ENABLE[MAX_PIPES];\
type DSCCLK0_DTO_DB_EN;\
type DSCCLK1_DTO_DB_EN;\
type DSCCLK2_DTO_DB_EN;\
type DSCCLK3_DTO_DB_EN;

struct dccg_shift {
DCCG_REG_FIELD_LIST(uint8_t)
DCCG3_REG_FIELD_LIST(uint8_t)
DCCG31_REG_FIELD_LIST(uint8_t)
DCCG314_REG_FIELD_LIST(uint8_t)
DCCG32_REG_FIELD_LIST(uint8_t)
DCCG35_REG_FIELD_LIST(uint8_t)
DCCG401_REG_FIELD_LIST(uint8_t)
};

struct dccg_mask {
Expand All @@ -345,6 +369,7 @@ struct dccg_mask {
DCCG314_REG_FIELD_LIST(uint32_t)
DCCG32_REG_FIELD_LIST(uint32_t)
DCCG35_REG_FIELD_LIST(uint32_t)
DCCG401_REG_FIELD_LIST(uint32_t)
};

struct dccg_registers {
Expand Down Expand Up @@ -392,6 +417,8 @@ struct dccg_registers {
uint32_t SYMCLKC_CLOCK_ENABLE;
uint32_t SYMCLKD_CLOCK_ENABLE;
uint32_t SYMCLKE_CLOCK_ENABLE;
uint32_t DP_DTO_MODULO[MAX_PIPES];
uint32_t DP_DTO_PHASE[MAX_PIPES];
};

struct dcn_dccg {
Expand Down
35 changes: 32 additions & 3 deletions drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
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Original file line number Diff line number Diff line change
Expand Up @@ -167,6 +167,15 @@
uint32_t DCHUBP_VMPG_CONFIG;\
uint32_t UCLK_PSTATE_FORCE

#define DCN401_HUBP_REG_COMMON_VARIABLE_LIST \
DCN32_HUBP_REG_COMMON_VARIABLE_LIST;\
uint32_t _3DLUT_FL_BIAS_SCALE;\
uint32_t _3DLUT_FL_CONFIG;\
uint32_t HUBP_3DLUT_ADDRESS_HIGH;\
uint32_t HUBP_3DLUT_ADDRESS_LOW;\
uint32_t HUBP_3DLUT_CONTROL;\
uint32_t HUBP_3DLUT_DLG_PARAM;\

#define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \
DCN_HUBP_REG_FIELD_BASE_LIST(type); \
type DMDATA_ADDRESS_HIGH;\
Expand Down Expand Up @@ -241,16 +250,36 @@
type CURSOR_UCLK_PSTATE_FORCE_EN; \
type CURSOR_UCLK_PSTATE_FORCE_VALUE

#define DCN401_HUBP_REG_FIELD_VARIABLE_LIST(type) \
DCN32_HUBP_REG_FIELD_VARIABLE_LIST(type);\
type MALL_PREF_CMD_TYPE; \
type MALL_PREF_MODE; \
type HUBP0_3DLUT_FL_MODE; \
type HUBP0_3DLUT_FL_FORMAT; \
type HUBP0_3DLUT_FL_SCALE; \
type HUBP0_3DLUT_FL_BIAS; \
type HUBP_3DLUT_ENABLE;\
type HUBP_3DLUT_DONE;\
type HUBP_3DLUT_ADDRESSING_MODE;\
type HUBP_3DLUT_WIDTH;\
type HUBP_3DLUT_TMZ;\
type HUBP_3DLUT_CROSSBAR_SELECT_Y_G;\
type HUBP_3DLUT_CROSSBAR_SELECT_CB_B;\
type HUBP_3DLUT_CROSSBAR_SELECT_CR_R;\
type HUBP_3DLUT_ADDRESS_HIGH;\
type HUBP_3DLUT_ADDRESS_LOW;\
type REFCYC_PER_3DLUT_GROUP;\

struct dcn_hubp2_registers {
DCN32_HUBP_REG_COMMON_VARIABLE_LIST;
DCN401_HUBP_REG_COMMON_VARIABLE_LIST;
};

struct dcn_hubp2_shift {
DCN32_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
DCN401_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
};

struct dcn_hubp2_mask {
DCN32_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
DCN401_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
};

struct dcn20_hubp {
Expand Down
11 changes: 11 additions & 0 deletions drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -78,6 +78,7 @@
SRI(DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id),\
SRI(DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id),\
SRI(DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id),\
SRI(DSCC_TEST_DEBUG_BUS_ROTATE, DSCC, id),\
SRI(DSCCIF_CONFIG0, DSCCIF, id),\
SRI(DSCCIF_CONFIG1, DSCCIF, id),\
SRI(DSCRM_DSC_FORWARD_CONFIG, DSCRM, id)
Expand All @@ -95,6 +96,7 @@
DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DISPCLK_R_GATE_DIS, mask_sh), \
DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DSCCLK_R_GATE_DIS, mask_sh), \
DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_DBG_EN, mask_sh), \
DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_TEST_CLOCK_MUX_SEL, mask_sh), \
DSC_SF(DSCC0_DSCC_CONFIG0, ICH_RESET_AT_END_OF_LINE, mask_sh), \
DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_PER_LINE, mask_sh), \
DSC_SF(DSCC0_DSCC_CONFIG0, ALTERNATE_ICH_ENCODING_EN, mask_sh), \
Expand Down Expand Up @@ -247,6 +249,10 @@
DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, mask_sh), \
DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, mask_sh), \
DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, mask_sh), \
DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS0_ROTATE, mask_sh), \
DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS1_ROTATE, mask_sh), \
DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS2_ROTATE, mask_sh), \
DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS3_ROTATE, mask_sh), \
DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, mask_sh), \
DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, mask_sh), \
Expand Down Expand Up @@ -421,6 +427,10 @@
type DSCC_UPDATE_PENDING_STATUS; \
type DSCC_UPDATE_TAKEN_STATUS; \
type DSCC_UPDATE_TAKEN_ACK; \
type DSCC_TEST_DEBUG_BUS0_ROTATE; \
type DSCC_TEST_DEBUG_BUS1_ROTATE; \
type DSCC_TEST_DEBUG_BUS2_ROTATE; \
type DSCC_TEST_DEBUG_BUS3_ROTATE; \
type DSCC_RATE_BUFFER0_FULLNESS_LEVEL; \
type DSCC_RATE_BUFFER1_FULLNESS_LEVEL; \
type DSCC_RATE_BUFFER2_FULLNESS_LEVEL; \
Expand Down Expand Up @@ -492,6 +502,7 @@ struct dcn20_dsc_registers {
uint32_t DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL;
uint32_t DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL;
uint32_t DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL;
uint32_t DSCC_TEST_DEBUG_BUS_ROTATE;
uint32_t DSCCIF_CONFIG0;
uint32_t DSCCIF_CONFIG1;
uint32_t DSCRM_DSC_FORWARD_CONFIG;
Expand Down
24 changes: 24 additions & 0 deletions drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -684,6 +684,14 @@ struct dce_hwseq_registers {
uint32_t DMU_CLK_CNTL;
uint32_t DCCG_GATE_DISABLE_CNTL4;
uint32_t DCCG_GATE_DISABLE_CNTL5;
uint32_t DOMAIN22_PG_CONFIG;
uint32_t DOMAIN23_PG_CONFIG;
uint32_t DOMAIN24_PG_CONFIG;
uint32_t DOMAIN25_PG_CONFIG;
uint32_t DOMAIN22_PG_STATUS;
uint32_t DOMAIN23_PG_STATUS;
uint32_t DOMAIN24_PG_STATUS;
uint32_t DOMAIN25_PG_STATUS;
};
/* set field name */
#define HWS_SF(blk_name, reg_name, field_name, post_fix)\
Expand Down Expand Up @@ -1214,13 +1222,28 @@ struct dce_hwseq_registers {
type DPIASYMCLK2_GATE_DISABLE;\
type DPIASYMCLK3_GATE_DISABLE;

#define HWSEQ_DCN401_REG_FIELD_LIST(type) \
type DOMAIN22_POWER_FORCEON; \
type DOMAIN22_POWER_GATE; \
type DOMAIN23_POWER_FORCEON; \
type DOMAIN23_POWER_GATE; \
type DOMAIN24_POWER_FORCEON; \
type DOMAIN24_POWER_GATE; \
type DOMAIN25_POWER_FORCEON; \
type DOMAIN25_POWER_GATE; \
type DOMAIN22_PGFSM_PWR_STATUS; \
type DOMAIN23_PGFSM_PWR_STATUS; \
type DOMAIN24_PGFSM_PWR_STATUS; \
type DOMAIN25_PGFSM_PWR_STATUS; \
type DOMAIN_DESIRED_PWR_STATE;
struct dce_hwseq_shift {
HWSEQ_REG_FIELD_LIST(uint8_t)
HWSEQ_DCN_REG_FIELD_LIST(uint8_t)
HWSEQ_DCN3_REG_FIELD_LIST(uint8_t)
HWSEQ_DCN301_REG_FIELD_LIST(uint8_t)
HWSEQ_DCN31_REG_FIELD_LIST(uint8_t)
HWSEQ_DCN35_REG_FIELD_LIST(uint8_t)
HWSEQ_DCN401_REG_FIELD_LIST(uint8_t)
};

struct dce_hwseq_mask {
Expand All @@ -1230,6 +1253,7 @@ struct dce_hwseq_mask {
HWSEQ_DCN301_REG_FIELD_LIST(uint32_t)
HWSEQ_DCN31_REG_FIELD_LIST(uint32_t)
HWSEQ_DCN35_REG_FIELD_LIST(uint32_t)
HWSEQ_DCN401_REG_FIELD_LIST(uint32_t)
};


Expand Down
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