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arm64/gcs: Add manual encodings of GCS instructions
Define C callable functions for GCS instructions used by the kernel. In order to avoid ambitious toolchain requirements for GCS support these are manually encoded, this means we have fixed register numbers which will be a bit limiting for the compiler but none of these should be used in sufficiently fast paths for this to be a problem. Note that GCSSTTR is used to store to EL0. Reviewed-by: Thiago Jung Bauermann <thiago.bauermann@linaro.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20241001-arm64-gcs-v13-9-222b78d87eee@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Mark Brown
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Catalin Marinas
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Oct 4, 2024
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/* SPDX-License-Identifier: GPL-2.0-only */ | ||
/* | ||
* Copyright (C) 2023 ARM Ltd. | ||
*/ | ||
#ifndef __ASM_GCS_H | ||
#define __ASM_GCS_H | ||
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#include <asm/types.h> | ||
#include <asm/uaccess.h> | ||
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static inline void gcsb_dsync(void) | ||
{ | ||
asm volatile(".inst 0xd503227f" : : : "memory"); | ||
} | ||
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static inline void gcsstr(u64 *addr, u64 val) | ||
{ | ||
register u64 *_addr __asm__ ("x0") = addr; | ||
register long _val __asm__ ("x1") = val; | ||
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/* GCSSTTR x1, x0 */ | ||
asm volatile( | ||
".inst 0xd91f1c01\n" | ||
: | ||
: "rZ" (_val), "r" (_addr) | ||
: "memory"); | ||
} | ||
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static inline void gcsss1(u64 Xt) | ||
{ | ||
asm volatile ( | ||
"sys #3, C7, C7, #2, %0\n" | ||
: | ||
: "rZ" (Xt) | ||
: "memory"); | ||
} | ||
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static inline u64 gcsss2(void) | ||
{ | ||
u64 Xt; | ||
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asm volatile( | ||
"SYSL %0, #3, C7, C7, #3\n" | ||
: "=r" (Xt) | ||
: | ||
: "memory"); | ||
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return Xt; | ||
} | ||
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#endif |
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