drm/nouveau: store supported dma mask in vmmgr

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
mariux64 · Oct 3, 2012 · dc73b45 · dc73b45
1 parent c0abf5c
commit dc73b45
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Showing 7 changed files with 9 additions and 7 deletions.
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/vm.h b/drivers/gpu/drm/nouveau/core/include/subdev/vm.h
@@ -69,6 +69,7 @@ struct nouveau_vmmgr {
 	struct nouveau_subdev base;
 
 	u64 limit;
+	u8  dma_bits;
 	u32 pgt_bits;
 	u8  spg_shift;
 	u8  lpg_shift;

diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.c
@@ -97,6 +97,7 @@ nv04_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 
 	priv->base.create = nv04_vm_create;
 	priv->base.limit = NV04_PDMA_SIZE;
+	priv->base.dma_bits = 32;
 	priv->base.pgt_bits = 32 - 12;
 	priv->base.spg_shift = 12;
 	priv->base.lpg_shift = 12;

diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c
@@ -98,6 +98,7 @@ nv41_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 
 	priv->base.create = nv04_vm_create;
 	priv->base.limit = NV41_GART_SIZE;
+	priv->base.dma_bits = 39;
 	priv->base.pgt_bits = 32 - 12;
 	priv->base.spg_shift = 12;
 	priv->base.lpg_shift = 12;

diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv44.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nv44.c
@@ -179,6 +179,7 @@ nv44_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 
 	priv->base.create = nv04_vm_create;
 	priv->base.limit = NV44_GART_SIZE;
+	priv->base.dma_bits = 39;
 	priv->base.pgt_bits = 32 - 12;
 	priv->base.spg_shift = 12;
 	priv->base.lpg_shift = 12;

diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c
@@ -201,6 +201,7 @@ nv50_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 		return ret;
 
 	priv->base.limit = 1ULL << 40;
+	priv->base.dma_bits = 40;
 	priv->base.pgt_bits  = 29 - 12;
 	priv->base.spg_shift = 12;
 	priv->base.lpg_shift = 16;

diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c
@@ -163,6 +163,7 @@ nvc0_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 		return ret;
 
 	priv->base.limit = 1ULL << 40;
+	priv->base.dma_bits = 40;
 	priv->base.pgt_bits  = 27 - 12;
 	priv->base.spg_shift = 12;
 	priv->base.lpg_shift = 17;

diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c
@@ -340,14 +340,10 @@ nouveau_ttm_init(struct nouveau_drm *drm)
 	u32 bits;
 	int ret;
 
-	if (nv_device(drm->device)->card_type >= NV_50) {
-		if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
-			bits = 40;
-		else
-			bits = 32;
-	} else {
+	bits = nouveau_vmmgr(drm->device)->dma_bits;
+	if ( drm->agp.stat == ENABLED ||
+	    !pci_dma_supported(dev->pdev, DMA_BIT_MASK(bits)))
 		bits = 32;
-	}
 
 	ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(bits));
 	if (ret)