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Merge tag 'renesas-r8a7740-ccf-and-timers-for-v3.18' into dt-timers-f…
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…or-v3.18

Renesas ARM Based SoC R8a7740 CCF and Timers Updates for v3.18

When booting using the r8a7740/armadillo800eva using dt-reference:
* Use CCF to initialise clocks via DT
* Initialise timers via DT
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Simon Horman committed Sep 9, 2014
2 parents 9dddfcf + 4333067 commit dcc683a
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Showing 6 changed files with 317 additions and 19 deletions.
17 changes: 17 additions & 0 deletions arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -178,6 +178,23 @@
};
};

&extal1_clk {
clock-frequency = <25000000>;
};
&extal2_clk {
clock-frequency = <48000000>;
};
&fsibck_clk {
clock-frequency = <12288000>;
};
&cpg_clocks {
renesas,mode = <0x05>; /* MD_CK0 | MD_CK2 */
};

&cmt1 {
status = "ok";
};

&i2c0 {
status = "okay";
touchscreen@55 {
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220 changes: 219 additions & 1 deletion arch/arm/boot/dts/r8a7740.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@

/include/ "skeleton.dtsi"

#include <dt-bindings/clock/r8a7740-clock.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
Expand Down Expand Up @@ -40,6 +41,18 @@
interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
};

cmt1: timer@e6138000 {
compatible = "renesas,cmt-48";
reg = <0xe6138000 0x170>;
interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
clock-names = "fck";

renesas,channels-mask = <0x3f>;

status = "disabled";
};

/* irqpin0: IRQ0 - IRQ7 */
irqpin0: irqpin@e6900000 {
compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
Expand Down Expand Up @@ -125,7 +138,7 @@
reg = <0xe9a00000 0x800>,
<0xe9a01800 0x800>;
interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
/* clocks = <&mstp3_clks R8A7740_CLK_GETHER>; */
clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
phy-mode = "mii";
#address-cells = <1>;
#size-cells = <0>;
Expand All @@ -141,6 +154,7 @@
0 202 IRQ_TYPE_LEVEL_HIGH
0 203 IRQ_TYPE_LEVEL_HIGH
0 204 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
status = "disabled";
};

Expand All @@ -153,69 +167,88 @@
0 71 IRQ_TYPE_LEVEL_HIGH
0 72 IRQ_TYPE_LEVEL_HIGH
0 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
status = "disabled";
};

scifa0: serial@e6c40000 {
compatible = "renesas,scifa-r8a7740", "renesas,scifa";
reg = <0xe6c40000 0x100>;
interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
clock-names = "sci_ick";
status = "disabled";
};

scifa1: serial@e6c50000 {
compatible = "renesas,scifa-r8a7740", "renesas,scifa";
reg = <0xe6c50000 0x100>;
interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
clock-names = "sci_ick";
status = "disabled";
};

scifa2: serial@e6c60000 {
compatible = "renesas,scifa-r8a7740", "renesas,scifa";
reg = <0xe6c60000 0x100>;
interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
clock-names = "sci_ick";
status = "disabled";
};

scifa3: serial@e6c70000 {
compatible = "renesas,scifa-r8a7740", "renesas,scifa";
reg = <0xe6c70000 0x100>;
interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
clock-names = "sci_ick";
status = "disabled";
};

scifa4: serial@e6c80000 {
compatible = "renesas,scifa-r8a7740", "renesas,scifa";
reg = <0xe6c80000 0x100>;
interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
clock-names = "sci_ick";
status = "disabled";
};

scifa5: serial@e6cb0000 {
compatible = "renesas,scifa-r8a7740", "renesas,scifa";
reg = <0xe6cb0000 0x100>;
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
clock-names = "sci_ick";
status = "disabled";
};

scifa6: serial@e6cc0000 {
compatible = "renesas,scifa-r8a7740", "renesas,scifa";
reg = <0xe6cc0000 0x100>;
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
clock-names = "sci_ick";
status = "disabled";
};

scifa7: serial@e6cd0000 {
compatible = "renesas,scifa-r8a7740", "renesas,scifa";
reg = <0xe6cd0000 0x100>;
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
clock-names = "sci_ick";
status = "disabled";
};

scifb8: serial@e6c30000 {
compatible = "renesas,scifb-r8a7740", "renesas,scifb";
reg = <0xe6c30000 0x100>;
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
clock-names = "sci_ick";
status = "disabled";
};

Expand All @@ -239,6 +272,7 @@
tpu: pwm@e6600000 {
compatible = "renesas,tpu-r8a7740", "renesas,tpu";
reg = <0xe6600000 0x100>;
clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
status = "disabled";
#pwm-cells = <3>;
};
Expand All @@ -248,6 +282,7 @@
reg = <0xe6bd0000 0x100>;
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH
0 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7740_CLK_MMC>;
status = "disabled";
};

Expand All @@ -257,6 +292,7 @@
interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH
0 118 IRQ_TYPE_LEVEL_HIGH
0 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
cap-sd-highspeed;
cap-sdio-irq;
status = "disabled";
Expand All @@ -268,6 +304,7 @@
interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH
0 122 IRQ_TYPE_LEVEL_HIGH
0 123 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
cap-sd-highspeed;
cap-sdio-irq;
status = "disabled";
Expand All @@ -279,6 +316,7 @@
interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH
0 126 IRQ_TYPE_LEVEL_HIGH
0 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
cap-sd-highspeed;
cap-sdio-irq;
status = "disabled";
Expand All @@ -289,6 +327,186 @@
compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
reg = <0xfe1f0000 0x400>;
interrupts = <0 9 0x4>;
clocks = <&mstp3_clks R8A7740_CLK_FSI>;
status = "disabled";
};

clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;

/* External root clock */
extalr_clk: extalr_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "extalr";
};
extal1_clk: extal1_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "extal1";
};
extal2_clk: extal2_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "extal2";
};
dv_clk: dv_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
clock-output-names = "dv";
};
fsiack_clk: fsiack_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "fsiack";
};
fsibck_clk: fsibck_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "fsibck";
};

/* Special CPG clocks */
cpg_clocks: cpg_clocks@e6150000 {
compatible = "renesas,r8a7740-cpg-clocks";
reg = <0xe6150000 0x10000>;
clocks = <&extal1_clk>, <&extalr_clk>;
#clock-cells = <1>;
clock-output-names = "system", "pllc0", "pllc1",
"pllc2", "r",
"usb24s",
"i", "zg", "b", "m1", "hp",
"hpp", "usbp", "s", "zb", "m3",
"cp";
};

/* Variable factor clocks (DIV6) */
sub_clk: sub_clk@e6150080 {
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150080 4>;
clocks = <&pllc1_div2_clk>;
#clock-cells = <0>;
clock-output-names = "sub";
};

/* Fixed factor clocks */
pllc1_div2_clk: pllc1_div2_clk {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "pllc1_div2";
};
extal1_div2_clk: extal1_div2_clk {
compatible = "fixed-factor-clock";
clocks = <&extal1_clk>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "extal1_div2";
};

/* Gate clocks */
subck_clks: subck_clks@e6150080 {
compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xe6150080 4>;
clocks = <&sub_clk>, <&sub_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
>;
clock-output-names =
"subck", "subck2";
};
mstp1_clks: mstp1_clks@e6150134 {
compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xe6150134 4>, <0xe6150038 4>;
clocks = <&cpg_clocks R8A7740_CLK_S>,
<&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
<&cpg_clocks R8A7740_CLK_B>,
<&sub_clk>, <&sub_clk>,
<&cpg_clocks R8A7740_CLK_B>;
#clock-cells = <1>;
renesas,clock-indices = <
R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
R8A7740_CLK_LCDC0
>;
clock-output-names =
"ceu21", "ceu20", "tmu0", "lcdc1", "iic0",
"tmu1", "lcdc0";
};
mstp2_clks: mstp2_clks@e6150138 {
compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xe6150138 4>, <0xe6150040 4>;
clocks = <&sub_clk>, <&sub_clk>,
<&cpg_clocks R8A7740_CLK_HP>,
<&cpg_clocks R8A7740_CLK_HP>,
<&cpg_clocks R8A7740_CLK_HP>,
<&cpg_clocks R8A7740_CLK_HP>,
<&sub_clk>, <&sub_clk>, <&sub_clk>,
<&sub_clk>, <&sub_clk>, <&sub_clk>,
<&sub_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
R8A7740_CLK_SCIFA6 R8A7740_CLK_SCIFA7
R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1
R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3
R8A7740_CLK_SCIFA4
>;
clock-output-names =
"scifa6", "scifa7", "dmac1", "dmac2", "dmac3",
"usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
"scifa2", "scifa3", "scifa4";
};
mstp3_clks: mstp3_clks@e615013c {
compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xe615013c 4>, <0xe6150048 4>;
clocks = <&cpg_clocks R8A7740_CLK_R>,
<&cpg_clocks R8A7740_CLK_HP>,
<&sub_clk>,
<&cpg_clocks R8A7740_CLK_HP>,
<&cpg_clocks R8A7740_CLK_HP>,
<&cpg_clocks R8A7740_CLK_HP>,
<&cpg_clocks R8A7740_CLK_HP>,
<&cpg_clocks R8A7740_CLK_HP>,
<&cpg_clocks R8A7740_CLK_HP>;
#clock-cells = <1>;
renesas,clock-indices = <
R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
>;
clock-output-names =
"cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1",
"mmc", "gether", "tpu0";
};
mstp4_clks: mstp4_clks@e6150140 {
compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xe6150140 4>, <0xe615004c 4>;
clocks = <&cpg_clocks R8A7740_CLK_HP>,
<&cpg_clocks R8A7740_CLK_HP>,
<&cpg_clocks R8A7740_CLK_HP>,
<&cpg_clocks R8A7740_CLK_HP>;
#clock-cells = <1>;
renesas,clock-indices = <
R8A7740_CLK_USBH R8A7740_CLK_SDHI2
R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
>;
clock-output-names =
"usbhost", "sdhi2", "usbfunc", "usphy";
};
};
};
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