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iio: frequency: adf4371: Add support for output stage mute
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Another feature of the ADF4371/ADF4372 is that the supply current to the
RF8P and RF8N output stage can shut down until the ADF4371 achieves lock
as measured by the digital lock detect circuitry. The mute to lock
detect bit (MUTE_LD) in REG25 enables this function.

Signed-off-by: Stefan Popa <stefan.popa@analog.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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Stefan Popa authored and Jonathan Cameron committed Jun 26, 2019
1 parent 84ed648 commit def914a
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7 changes: 7 additions & 0 deletions Documentation/devicetree/bindings/iio/frequency/adf4371.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,13 @@ properties:
Must be "clkin"
maxItems: 1

adi,mute-till-lock-en:
type: boolean
description:
If this property is present, then the supply current to RF8P and RF8N
output stage will shut down until the ADF4371/ADF4372 achieves lock as
measured by the digital lock detect circuitry.

required:
- compatible
- reg
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13 changes: 13 additions & 0 deletions drivers/iio/frequency/adf4371.c
Original file line number Diff line number Diff line change
Expand Up @@ -45,6 +45,10 @@
#define ADF4371_RF_DIV_SEL_MSK GENMASK(6, 4)
#define ADF4371_RF_DIV_SEL(x) FIELD_PREP(ADF4371_RF_DIV_SEL_MSK, x)

/* ADF4371_REG25 */
#define ADF4371_MUTE_LD_MSK BIT(7)
#define ADF4371_MUTE_LD(x) FIELD_PREP(ADF4371_MUTE_LD_MSK, x)

/* ADF4371_REG32 */
#define ADF4371_TIMEOUT_MSK GENMASK(1, 0)
#define ADF4371_TIMEOUT(x) FIELD_PREP(ADF4371_TIMEOUT_MSK, x)
Expand Down Expand Up @@ -484,6 +488,15 @@ static int adf4371_setup(struct adf4371_state *st)
if (ret < 0)
return ret;

/* Mute to Lock Detect */
if (device_property_read_bool(&st->spi->dev, "adi,mute-till-lock-en")) {
ret = regmap_update_bits(st->regmap, ADF4371_REG(0x25),
ADF4371_MUTE_LD_MSK,
ADF4371_MUTE_LD(1));
if (ret < 0)
return ret;
}

/* Set address in ascending order, so the bulk_write() will work */
ret = regmap_update_bits(st->regmap, ADF4371_REG(0x0),
ADF4371_ADDR_ASC_MSK | ADF4371_ADDR_ASC_R_MSK,
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