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Hexagon: Add hypervisor interface
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Signed-off-by: Richard Kuo <rkuo@codeaurora.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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Richard Kuo authored and Linus Torvalds committed Nov 1, 2011
1 parent c150290 commit e49ee29
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281 changes: 281 additions & 0 deletions arch/hexagon/include/asm/hexagon_vm.h
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/*
* Declarations for to Hexagon Virtal Machine.
*
* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/

#ifndef ASM_HEXAGON_VM_H
#define ASM_HEXAGON_VM_H

/*
* In principle, a Linux kernel for the VM could
* selectively define the virtual instructions
* as inline assembler macros, but for a first pass,
* we'll use subroutines for both the VM and the native
* kernels. It's costing a subroutine call/return,
* but it makes for a single set of entry points
* for tracing/debugging.
*/

/*
* Lets make this stuff visible only if configured,
* so we can unconditionally include the file.
*/

#ifndef __ASSEMBLY__

enum VM_CACHE_OPS {
ickill,
dckill,
l2kill,
dccleaninva,
icinva,
idsync,
fetch_cfg
};

enum VM_INT_OPS {
nop,
globen,
globdis,
locen,
locdis,
affinity,
get,
peek,
status,
post,
clear
};

extern void _K_VM_event_vector(void);

void __vmrte(void);
long __vmsetvec(void *);
long __vmsetie(long);
long __vmgetie(void);
long __vmintop(enum VM_INT_OPS, long, long, long, long);
long __vmclrmap(void *, unsigned long);
long __vmnewmap(void *);
long __vmcache(enum VM_CACHE_OPS op, unsigned long addr, unsigned long len);
unsigned long long __vmgettime(void);
long __vmsettime(unsigned long long);
long __vmstart(void *, void *);
void __vmstop(void);
long __vmwait(void);
void __vmyield(void);
long __vmvpid(void);

static inline long __vmcache_ickill(void)
{
return __vmcache(ickill, 0, 0);
}

static inline long __vmcache_dckill(void)
{
return __vmcache(dckill, 0, 0);
}

static inline long __vmcache_l2kill(void)
{
return __vmcache(l2kill, 0, 0);
}

static inline long __vmcache_dccleaninva(unsigned long addr, unsigned long len)
{
return __vmcache(dccleaninva, addr, len);
}

static inline long __vmcache_icinva(unsigned long addr, unsigned long len)
{
return __vmcache(icinva, addr, len);
}

static inline long __vmcache_idsync(unsigned long addr,
unsigned long len)
{
return __vmcache(idsync, addr, len);
}

static inline long __vmcache_fetch_cfg(unsigned long val)
{
return __vmcache(fetch_cfg, val, 0);
}

/* interrupt operations */

static inline long __vmintop_nop(void)
{
return __vmintop(nop, 0, 0, 0, 0);
}

static inline long __vmintop_globen(long i)
{
return __vmintop(globen, i, 0, 0, 0);
}

static inline long __vmintop_globdis(long i)
{
return __vmintop(globdis, i, 0, 0, 0);
}

static inline long __vmintop_locen(long i)
{
return __vmintop(locen, i, 0, 0, 0);
}

static inline long __vmintop_locdis(long i)
{
return __vmintop(locdis, i, 0, 0, 0);
}

static inline long __vmintop_affinity(long i, long cpu)
{
return __vmintop(locdis, i, cpu, 0, 0);
}

static inline long __vmintop_get(void)
{
return __vmintop(get, 0, 0, 0, 0);
}

static inline long __vmintop_peek(void)
{
return __vmintop(peek, 0, 0, 0, 0);
}

static inline long __vmintop_status(long i)
{
return __vmintop(status, i, 0, 0, 0);
}

static inline long __vmintop_post(long i)
{
return __vmintop(post, i, 0, 0, 0);
}

static inline long __vmintop_clear(long i)
{
return __vmintop(clear, i, 0, 0, 0);
}

#else /* Only assembly code should reference these */

#define HVM_TRAP1_VMRTE 1
#define HVM_TRAP1_VMSETVEC 2
#define HVM_TRAP1_VMSETIE 3
#define HVM_TRAP1_VMGETIE 4
#define HVM_TRAP1_VMINTOP 5
#define HVM_TRAP1_VMCLRMAP 10
#define HVM_TRAP1_VMNEWMAP 11
#define HVM_TRAP1_FORMERLY_VMWIRE 12
#define HVM_TRAP1_VMCACHE 13
#define HVM_TRAP1_VMGETTIME 14
#define HVM_TRAP1_VMSETTIME 15
#define HVM_TRAP1_VMWAIT 16
#define HVM_TRAP1_VMYIELD 17
#define HVM_TRAP1_VMSTART 18
#define HVM_TRAP1_VMSTOP 19
#define HVM_TRAP1_VMVPID 20
#define HVM_TRAP1_VMSETREGS 21
#define HVM_TRAP1_VMGETREGS 22

#endif /* __ASSEMBLY__ */

/*
* Constants for virtual instruction parameters and return values
*/

/* vmsetie arguments */

#define VM_INT_DISABLE 0
#define VM_INT_ENABLE 1

/* vmsetimask arguments */

#define VM_INT_UNMASK 0
#define VM_INT_MASK 1

#define VM_NEWMAP_TYPE_LINEAR 0
#define VM_NEWMAP_TYPE_PGTABLES 1


/*
* Event Record definitions useful to both C and Assembler
*/

/* VMEST Layout */

#define HVM_VMEST_UM_SFT 31
#define HVM_VMEST_UM_MSK 1
#define HVM_VMEST_IE_SFT 30
#define HVM_VMEST_IE_MSK 1
#define HVM_VMEST_EVENTNUM_SFT 16
#define HVM_VMEST_EVENTNUM_MSK 0xff
#define HVM_VMEST_CAUSE_SFT 0
#define HVM_VMEST_CAUSE_MSK 0xffff

/*
* The initial program gets to find a system environment descriptor
* on its stack when it begins exection. The first word is a version
* code to indicate what is there. Zero means nothing more.
*/

#define HEXAGON_VM_SED_NULL 0

/*
* Event numbers for vector binding
*/

#define HVM_EV_RESET 0
#define HVM_EV_MACHCHECK 1
#define HVM_EV_GENEX 2
#define HVM_EV_TRAP 8
#define HVM_EV_INTR 15
/* These shoud be nuked as soon as we know the VM is up to spec v0.1.1 */
#define HVM_EV_INTR_0 16
#define HVM_MAX_INTR 240

/*
* Cause values for General Exception
*/

#define HVM_GE_C_BUS 0x01
#define HVM_GE_C_XPROT 0x11
#define HVM_GE_C_XUSER 0x14
#define HVM_GE_C_INVI 0x15
#define HVM_GE_C_PRIVI 0x1B
#define HVM_GE_C_XMAL 0x1C
#define HVM_GE_C_RMAL 0x20
#define HVM_GE_C_WMAL 0x21
#define HVM_GE_C_RPROT 0x22
#define HVM_GE_C_WPROT 0x23
#define HVM_GE_C_RUSER 0x24
#define HVM_GE_C_WUSER 0x25
#define HVM_GE_C_CACHE 0x28

/*
* Cause codes for Machine Check
*/

#define HVM_MCHK_C_DOWN 0x00
#define HVM_MCHK_C_BADSP 0x01
#define HVM_MCHK_C_BADEX 0x02
#define HVM_MCHK_C_BADPT 0x03
#define HVM_MCHK_C_REGWR 0x29

#endif
111 changes: 111 additions & 0 deletions arch/hexagon/include/asm/vm_mmu.h
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/*
* Hexagon VM page table entry definitions
*
* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/

#ifndef _ASM_VM_MMU_H
#define _ASM_VM_MMU_H

/*
* Shift, mask, and other constants for the Hexagon Virtual Machine
* page tables.
*
* Virtual machine MMU allows first-level entries to either be
* single-level lookup PTEs for very large pages, or PDEs pointing
* to second-level PTEs for smaller pages. If PTE is single-level,
* the least significant bits cannot be used as software bits to encode
* virtual memory subsystem information about the page, and that state
* must be maintained in some parallel data structure.
*/

/* S or Page Size field in PDE */
#define __HVM_PDE_S (0x7 << 0)
#define __HVM_PDE_S_4KB 0
#define __HVM_PDE_S_16KB 1
#define __HVM_PDE_S_64KB 2
#define __HVM_PDE_S_256KB 3
#define __HVM_PDE_S_1MB 4
#define __HVM_PDE_S_4MB 5
#define __HVM_PDE_S_16MB 6
#define __HVM_PDE_S_INVALID 7

/* Masks for L2 page table pointer, as function of page size */
#define __HVM_PDE_PTMASK_4KB 0xfffff000
#define __HVM_PDE_PTMASK_16KB 0xfffffc00
#define __HVM_PDE_PTMASK_64KB 0xffffff00
#define __HVM_PDE_PTMASK_256KB 0xffffffc0
#define __HVM_PDE_PTMASK_1MB 0xfffffff0

/*
* Virtual Machine PTE Bits/Fields
*/
#define __HVM_PTE_T (1<<4)
#define __HVM_PTE_U (1<<5)
#define __HVM_PTE_C (0x7<<6)
#define __HVM_PTE_CVAL(pte) (((pte) & __HVM_PTE_C) >> 6)
#define __HVM_PTE_R (1<<9)
#define __HVM_PTE_W (1<<10)
#define __HVM_PTE_X (1<<11)

/*
* Cache Attributes, to be shifted as necessary for virtual/physical PTEs
*/

#define __HEXAGON_C_WB 0x0 /* Write-back, no L2 */
#define __HEXAGON_C_WT 0x1 /* Write-through, no L2 */
#define __HEXAGON_C_DEV 0x4 /* Device register space */
#define __HEXAGON_C_WT_L2 0x5 /* Write-through, with L2 */
/* this really should be #if CONFIG_HEXAGON_ARCH = 2 but that's not defined */
#if defined(CONFIG_HEXAGON_COMET) || defined(CONFIG_QDSP6_ST1)
#define __HEXAGON_C_UNC __HEXAGON_C_DEV
#else
#define __HEXAGON_C_UNC 0x6 /* Uncached memory */
#endif
#define __HEXAGON_C_WB_L2 0x7 /* Write-back, with L2 */

/*
* This can be overriden, but we're defaulting to the most aggressive
* cache policy, the better to find bugs sooner.
*/

#define CACHE_DEFAULT __HEXAGON_C_WB_L2

/* Masks for physical page address, as a function of page size */

#define __HVM_PTE_PGMASK_4KB 0xfffff000
#define __HVM_PTE_PGMASK_16KB 0xffffc000
#define __HVM_PTE_PGMASK_64KB 0xffff0000
#define __HVM_PTE_PGMASK_256KB 0xfffc0000
#define __HVM_PTE_PGMASK_1MB 0xfff00000

/* Masks for single-level large page lookups */

#define __HVM_PTE_PGMASK_4MB 0xffc00000
#define __HVM_PTE_PGMASK_16MB 0xff000000

/*
* "Big kernel page mappings" (see vm_init_segtable.S)
* are currently 16MB
*/

#define BIG_KERNEL_PAGE_SHIFT 24
#define BIG_KERNEL_PAGE_SIZE (1 << BIG_KERNEL_PAGE_SHIFT)



#endif /* _ASM_VM_MMU_H */
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