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clk: en7523: Rework clock handling for different clock numbers
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Airoha EN7581 SoC have additional clock compared to EN7523 but current
driver permits to only support up to EN7523 clock numbers.

To handle this, rework the clock handling and permit to declare the
clocks number in match_data and alloca clk_data based on the compatible
match_data.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20250113231030.6735-2-ansuelsmth@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Christian Marangi authored and Stephen Boyd committed Jan 13, 2025
1 parent 52fd170 commit e4a9748
Showing 1 changed file with 8 additions and 6 deletions.
14 changes: 8 additions & 6 deletions drivers/clk/clk-en7523.c
Original file line number Diff line number Diff line change
Expand Up @@ -75,6 +75,7 @@ struct en_rst_data {
};

struct en_clk_soc_data {
u32 num_clocks;
const struct clk_ops pcie_ops;
int (*hw_init)(struct platform_device *pdev,
struct clk_hw_onecell_data *clk_data);
Expand Down Expand Up @@ -504,8 +505,6 @@ static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_dat
u32 rate;
int i;

clk_data->num = EN7523_NUM_CLOCKS;

for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) {
const struct en_clk_desc *desc = &en7523_base_clks[i];
u32 reg = desc->div_reg ? desc->div_reg : desc->base_reg;
Expand Down Expand Up @@ -587,8 +586,6 @@ static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_dat

hw = en7523_register_pcie_clk(dev, base);
clk_data->hws[EN7523_CLK_PCIE] = hw;

clk_data->num = EN7523_NUM_CLOCKS;
}

static int en7523_reset_update(struct reset_controller_dev *rcdev,
Expand Down Expand Up @@ -702,13 +699,15 @@ static int en7523_clk_probe(struct platform_device *pdev)
struct clk_hw_onecell_data *clk_data;
int r;

soc_data = device_get_match_data(&pdev->dev);

clk_data = devm_kzalloc(&pdev->dev,
struct_size(clk_data, hws, EN7523_NUM_CLOCKS),
struct_size(clk_data, hws, soc_data->num_clocks),
GFP_KERNEL);
if (!clk_data)
return -ENOMEM;

soc_data = device_get_match_data(&pdev->dev);
clk_data->num = soc_data->num_clocks;
r = soc_data->hw_init(pdev, clk_data);
if (r)
return r;
Expand All @@ -717,6 +716,7 @@ static int en7523_clk_probe(struct platform_device *pdev)
}

static const struct en_clk_soc_data en7523_data = {
.num_clocks = ARRAY_SIZE(en7523_base_clks) + 1,
.pcie_ops = {
.is_enabled = en7523_pci_is_enabled,
.prepare = en7523_pci_prepare,
Expand All @@ -726,6 +726,8 @@ static const struct en_clk_soc_data en7523_data = {
};

static const struct en_clk_soc_data en7581_data = {
/* We increment num_clocks by 1 to account for additional PCIe clock */
.num_clocks = ARRAY_SIZE(en7581_base_clks) + 1,
.pcie_ops = {
.is_enabled = en7581_pci_is_enabled,
.enable = en7581_pci_enable,
Expand Down

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