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ASoC: rt5670: fix wrong bit def for pll src
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The bit allocation for PLL source is 0x80 [13:11] instead of [12:11]

Signed-off-by: Bard Liao <bardliao@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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Bard Liao authored and Mark Brown committed Nov 17, 2015
1 parent 8005c49 commit e71bf05
Showing 1 changed file with 6 additions and 6 deletions.
12 changes: 6 additions & 6 deletions sound/soc/codecs/rt5670.h
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Original file line number Diff line number Diff line change
Expand Up @@ -973,12 +973,12 @@
#define RT5670_SCLK_SRC_MCLK (0x0 << 14)
#define RT5670_SCLK_SRC_PLL1 (0x1 << 14)
#define RT5670_SCLK_SRC_RCCLK (0x2 << 14) /* 15MHz */
#define RT5670_PLL1_SRC_MASK (0x3 << 12)
#define RT5670_PLL1_SRC_SFT 12
#define RT5670_PLL1_SRC_MCLK (0x0 << 12)
#define RT5670_PLL1_SRC_BCLK1 (0x1 << 12)
#define RT5670_PLL1_SRC_BCLK2 (0x2 << 12)
#define RT5670_PLL1_SRC_BCLK3 (0x3 << 12)
#define RT5670_PLL1_SRC_MASK (0x7 << 11)
#define RT5670_PLL1_SRC_SFT 11
#define RT5670_PLL1_SRC_MCLK (0x0 << 11)
#define RT5670_PLL1_SRC_BCLK1 (0x1 << 11)
#define RT5670_PLL1_SRC_BCLK2 (0x2 << 11)
#define RT5670_PLL1_SRC_BCLK3 (0x3 << 11)
#define RT5670_PLL1_PD_MASK (0x1 << 3)
#define RT5670_PLL1_PD_SFT 3
#define RT5670_PLL1_PD_1 (0x0 << 3)
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