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arm64: dts: imx8: add adma lpcg clocks
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Add adma lpcg clocks

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Dong Aisheng authored and Shawn Guo committed Mar 29, 2021
1 parent 9de8a22 commit e783b6b
Showing 1 changed file with 122 additions and 0 deletions.
122 changes: 122 additions & 0 deletions arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -4,17 +4,51 @@
* Dong Aisheng <aisheng.dong@nxp.com>
*/

#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>

adma_subsys: bus@59000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x59000000 0x0 0x59000000 0x2000000>;

dma_ipg_clk: clock-dma-ipg {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <120000000>;
clock-output-names = "dma_ipg_clk";
};

/* LPCG clocks */
adma_lpcg: clock-controller@59000000 {
reg = <0x59000000 0x2000000>;
#clock-cells = <1>;
};

dsp_lpcg: clock-controller@59580000 {
reg = <0x59580000 0x10000>;
#clock-cells = <1>;
clocks = <&dma_ipg_clk>,
<&dma_ipg_clk>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_7>;
clock-output-names = "dsp_lpcg_adb_clk",
"dsp_lpcg_ipg_clk",
"dsp_lpcg_core_clk";
power-domains = <&pd IMX_SC_R_DSP>;
};

dsp_ram_lpcg: clock-controller@59590000 {
reg = <0x59590000 0x10000>;
#clock-cells = <1>;
clocks = <&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_4>;
clock-output-names = "dsp_ram_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_DSP_RAM>;
};

adma_dsp: dsp@596e8000 {
compatible = "fsl,imx8qxp-dsp";
reg = <0x596e8000 0x88000>;
Expand Down Expand Up @@ -76,6 +110,50 @@ adma_subsys: bus@59000000 {
status = "disabled";
};

uart0_lpcg: clock-controller@5a460000 {
reg = <0x5a460000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_ADMA_UART0_CLK>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "uart0_lpcg_baud_clk",
"uart0_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_UART_0>;
};

uart1_lpcg: clock-controller@5a470000 {
reg = <0x5a470000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_ADMA_UART1_CLK>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "uart1_lpcg_baud_clk",
"uart1_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_UART_1>;
};

uart2_lpcg: clock-controller@5a480000 {
reg = <0x5a480000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_ADMA_UART2_CLK>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "uart2_lpcg_baud_clk",
"uart2_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_UART_2>;
};

uart3_lpcg: clock-controller@5a490000 {
reg = <0x5a490000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_ADMA_UART3_CLK>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "uart3_lpcg_baud_clk",
"uart3_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_UART_3>;
};

adma_i2c0: i2c@5a800000 {
reg = <0x5a800000 0x4000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
Expand Down Expand Up @@ -119,4 +197,48 @@ adma_subsys: bus@59000000 {
power-domains = <&pd IMX_SC_R_I2C_3>;
status = "disabled";
};

i2c0_lpcg: clock-controller@5ac00000 {
reg = <0x5ac00000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_ADMA_I2C0_CLK>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "i2c0_lpcg_clk",
"i2c0_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_I2C_0>;
};

i2c1_lpcg: clock-controller@5ac10000 {
reg = <0x5ac10000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_ADMA_I2C1_CLK>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "i2c1_lpcg_clk",
"i2c1_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_I2C_1>;
};

i2c2_lpcg: clock-controller@5ac20000 {
reg = <0x5ac20000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_ADMA_I2C2_CLK>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "i2c2_lpcg_clk",
"i2c2_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_I2C_2>;
};

i2c3_lpcg: clock-controller@5ac30000 {
reg = <0x5ac30000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_ADMA_I2C3_CLK>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "i2c3_lpcg_clk",
"i2c3_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_I2C_3>;
};
};

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